PIC18F65J90-I/PT Microchip Technology, PIC18F65J90-I/PT Datasheet - Page 411

• Manufacturer Part Number: PIC18F65J90-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 51
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183030
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Timer0 .............................................................................. 137
Timer1 .............................................................................. 141
Timer2 .............................................................................. 147
Timer3 .............................................................................. 149
Timing Diagrams
 2010 Microchip Technology Inc.
Associated Registers ............................................... 139
Clock Source Select (T0CS Bit) ............................... 138
Operation ................................................................. 138
Overflow Interrupt .................................................... 139
Prescaler .................................................................. 139
Prescaler Assignment (PSA Bit) .............................. 139
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 139
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 138
Source Edge Select (T0SE Bit) ................................ 138
16-Bit Read/Write Mode ........................................... 143
Associated Registers ............................................... 145
Interrupt .................................................................... 144
Operation ................................................................. 142
Oscillator .......................................................... 141, 143
Oscillator, as Secondary Clock .................................. 37
Overflow Interrupt .................................................... 141
Resetting, Using the CCP Special
TMR1H Register ...................................................... 141
TMR1L Register ....................................................... 141
Use as a Clock Source ............................................ 143
Use as a Real-Time Clock ....................................... 144
Associated Registers ............................................... 148
Interrupt .................................................................... 148
Operation ................................................................. 147
Output ...................................................................... 148
PR2 Register ............................................................ 159
TMR2 to PR2 Match Interrupt .................................. 159
16-Bit Read/Write Mode ........................................... 151
Associated Registers ............................................... 151
Operation ................................................................. 150
Oscillator .......................................................... 149, 151
Overflow Interrupt ............................................ 149, 151
Special Event Trigger (CCP) .................................... 151
TMR3H Register ...................................................... 149
TMR3L Register ....................................................... 149
A/D Conversion ........................................................ 392
Acknowledge Sequence .......................................... 228
Asynchronous Reception ................................. 248, 265
Asynchronous Transmission ............................ 246, 263
Asynchronous Transmission
Automatic Baud Rate Calculation ............................ 244
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 249
Baud Rate Generator with Clock Arbitration ............ 222
BRG Overflow Sequence ......................................... 244
BRG Reset Due to SDA Arbitration During Start
Bus Collision During a Repeated Start
Bus Collision During a Repeated Start
Bus Collision During a Start Condition
Switching Assignment ...................................... 139
Layout Considerations ..................................... 144
Event Trigger ................................................... 144
(Back to Back) ......................................... 246, 263
Normal Operation ............................................ 249
Condition .......................................................... 231
Condition (Case 1) ........................................... 232
Condition (Case 2) ........................................... 232
(SCL = 0) ......................................................... 231
PIC18F85J90 FAMILY
Bus Collision During a Stop Condition (Case 1) ...... 233
Bus Collision During a Stop Condition (Case 2) ...... 233
Bus Collision During Start Condition (SDA Only) .... 230
Bus Collision for Transmit and Acknowledge .......... 229
Capture/Compare/PWM (CCP1,CCP2) ................... 381
CLKO and I/O .......................................................... 378
Clock Synchronization ............................................. 215
Clock/Instruction Cycle .............................................. 68
EUSART/AUSART Synchronous Receive
EUSART/AUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ..................... 382
Example SPI Master Mode (CKE = 1) ..................... 383
Example SPI Slave Mode (CKE = 0) ....................... 384
Example SPI Slave Mode (CKE = 1) ....................... 385
External Clock (All Modes Except PLL) ................... 376
Fail-Safe Clock Monitor ........................................... 302
First Start Bit Timing ................................................ 223
I
I
I
I
I
I
I
I
I
I
I
I
I
I
LCD Interrupt in Quarter Duty Cycle Drive .............. 186
LCD Sleep Entry/Exit When SLPEN = 1 or
MSSP I
MSSP I
PWM Output ............................................................ 159
Repeated Start Condition ........................................ 224
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................ 250
Slave Synchronization ............................................. 197
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ........................................ 196
SPI Mode (Slave Mode, CKE = 0) ........................... 198
SPI Mode (Slave Mode, CKE = 1) ........................... 198
Synchronous Reception
Synchronous Transmission ............................. 251, 266
Synchronous Transmission
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 380
Transition for Entry to Idle Mode ............................... 48
2
2
2
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 386
C Bus Start/Stop Bits ............................................ 386
C Master Mode (7 or 10-Bit Transmission) ........... 226
C Master Mode (7-Bit Reception) ......................... 227
C Slave Mode (10-Bit Reception, SEN = 0,
C Slave Mode (10-Bit Reception, SEN = 0) .......... 211
C Slave Mode (10-Bit Reception, SEN = 1) .......... 217
C Slave Mode (10-Bit Transmission) .................... 213
C Slave Mode (7-Bit Reception, SEN = 0,
C Slave Mode (7-Bit Reception, SEN = 0) ............ 208
C Slave Mode (7-Bit Reception, SEN = 1) ............ 216
C Slave Mode (7-Bit Transmission) ...................... 210
C Slave Mode General Call Address
C Stop Condition Receive or Transmit Mode ........ 228
(Master/Slave) ................................................. 390
(Master/Slave) ................................................. 390
ADMSK = 01001) ............................................ 212
ADMSK = 01011) ............................................ 209
Sequence (7 or 10-Bit Address Mode) ............ 218
CS1:CS0 = 00 ................................................. 187
Timer (OST) and Power-up Timer (PWRT) ..... 379
V
(Master Mode, SREN) ............................. 253, 268
(Through TXEN) ...................................... 252, 267
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
DD
2
2
C Bus Data ................................................ 388
C Bus Start/Stop Bits ................................. 388
Rise > T
PWRT
DD
) ............................................ 55
, V
DD
DD
DD
), Case 1 ...................... 54
), Case 2 ...................... 55
Rise T
DD
DS39770C-page 411
,
PWRT
) .............. 54