PIC18F65J90-I/PT Microchip Technology, PIC18F65J90-I/PT Datasheet - Page 390

• Manufacturer Part Number: PIC18F65J90-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J90-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 51
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183030
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F85J90 FAMILY
FIGURE 26-17:
TABLE 26-22: EUSART/AUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 26-18:
TABLE 26-23: EUSART/AUSART SYNCHRONOUS RECEIVE REQUIREMENTS
DS39770C-page 390
120
121
122
125
126
Param
Param.
No.
No.
Note:
RXx/DTx
TXx/CKx
Note:
T
T
T
RXx/DTx
TXx/CKx
T
T
CK
CKRF
Symbol
DTRF
CK
Symbol
DT
pin
pin
H2
L2
V2
pin
pin
Refer to Figure 26-3 for load conditions.
DT
DTL
CKL
V SYNC XMIT (MASTER and SLAVE)
Refer to Figure 26-3 for load conditions.
Clock High to Data Out Valid
Clock Out Rise Time and Fall Time (Master mode)
Data Out Rise Time and Fall Time
SYNC RCV (MASTER and SLAVE)
Data Hold before CKx  (DTx hold time)
Data Hold after CKx  (DTx hold time)
EUSART/AUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
EUSART/AUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
120
Characteristic
121
Characteristic
125
121
126
Min
10
15
Min
Max
—
—
—
—
—
122
Units
 2010 Microchip Technology Inc.
Max
ns
ns
20
40
20
Units
ns
ns
ns
Conditions
Conditions