AT90PWM3B-16MU Atmel, AT90PWM3B-16MU Datasheet - Page 262
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AT90PWM3B-16MU
Manufacturer Part Number
AT90PWM3B-16MU
Description
IC MCU AVR RISC 8K FLASH 32-QFN
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM3B-16SU.pdf
(361 pages)
Specifications of AT90PWM3B-16MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
27
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-QFN
Package
32QFN EP
Device Core
AVR
Family Name
90P
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
27
Interface Type
SPI/USART
On-chip Adc
11-chx10-bit
Number Of Timers
2
Processor Series
AT90PWMx
Core
AVR8
Data Ram Size
512 B
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
Minimum Operating Temperature
- 40 C
On-chip Dac
10 bit, 1 Channel
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRMC200 - KIT EVAL FOR AT90PWM3 ASYNCATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK520 - ADAPTER KIT FOR 90PWM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90PWM3B-16MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
AT90PWM3B-16MUR
Manufacturer:
TI
Quantity:
1 829
- Current page: 262 of 361
- Download datasheet (7Mb)
To work with the 10-bit DAC, two registers have to be updated. In order to avoid intermediate
value, the DAC input values which are really converted into analog signal are buffering into
unreachable registers. In normal mode, the update of the shadow register is done when the reg-
ister DACH is written.
In case DAATE bit is set, the DAC input values will be updated on the trigger event selected
through DATS bits.
In order to avoid wrong DAC input values, the update can only be done after having written
respectively DACL and DACH registers. It is possible to work on 8-bit configuration by only writ-
ing the DACH value. In this case, update is done each trigger event.
In case DAATE bit is cleared, the DAC is in an automatic update mode. Writing the DACH regis-
ter automatically update the DAC input values with the DACH and DACL register values.
It means that whatever is the configuration of the DAATE bit, changing the DACL register has no
effect on the DAC output until the DACH register has also been updated. So, to work with 10
bits, DACL must be written first before DACH. To work with 8-bit configuration, writing DACH
allows the update of the DAC.
AT90PWM2/3/2B/3B
262
4317J–AVR–08/10
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