AT90PWM3B-16MU Atmel, AT90PWM3B-16MU Datasheet - Page 194

• Manufacturer Part Number: AT90PWM3B-16MU
• Description: IC MCU AVR RISC 8K FLASH 32-QFN
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM3B-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-QFN
• Package: 32QFN EP
• Device Core: AVR
• Family Name: 90P
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 27
• Interface Type: SPI/USART
• On-chip Adc: 11-chx10-bit
• Number Of Timers: 2
• Processor Series: AT90PWMx
• Core: AVR8
• Data Ram Size: 512 B
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 10 bit, 1 Channel
• For Use With: ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRMC200 - KIT EVAL FOR AT90PWM3 ASYNCATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK520 - ADAPTER KIT FOR 90PWM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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AT90PWM2/3/2B/3B
Note:
Assembly Code Example
C Code Example
TABLE 2.
USART_Receive:
USART_ReceiveNoError:
unsigned int USART_Receive( void )
{
}
; Wait for data to be received
sbis UCSRA, RXC0
rjmp USART_Receive
; Get status and 9th bit, then data from buffer
lds
lds r17, UCSRB
lds r16, UDR
; If error, return -1
andi r18,(1<<FE0)|(1<<DOR0)|(1<<UPE0)
breq USART_ReceiveNoError
ldi
ldi
; Filter the 9th bit, then return
lsr
andi r17, 0x01
ret
unsigned char status, resh, resl;
/* Wait for data to be received */
while ( !(UCSRA & (1<<RXC0)) )
/* Get status and 9th bit, then data */
/* from buffer */
status = UCSRA;
resh = UCSRB;
resl = UDR;
/* If error, return -1 */
if ( status & (1<<FE0)|(1<<DOR0)|(1<<UPE0) )
/* Filter the 9th bit, then return */
resh = (resh >> 1) & 0x01;
return ((resh << 8) | resl);
1. The example code assumes that the part specific header file is included.
return -1;
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
r18, UCSRA
r17, HIGH(-1)
r16, LOW(-1)
r17
;
(1)
(1)
4317J–AVR–08/10