PIC18F1220-I/SS Microchip Technology, PIC18F1220-I/SS Datasheet - Page 8

• Manufacturer Part Number: PIC18F1220-I/SS
• Description: IC MCU FLASH 2KX16 A/D 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1220-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 4KB (2K x 16)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7-ch x 10-bit
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOPAC164018 - MODULE SKT PROMATEII 20SSOP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F1230/1330
2.4
Figure 2-7 shows the high-level overview of the
programming process. First, a Bulk Erase is performed.
Next, the code memory, ID locations and data
EEPROM are programmed (see Section 3.3 “Data
EEPROM Programming”). These memories are then
verified to ensure that programming was successful. If
no errors are detected, the Configuration bits are then
programmed and verified.
FIGURE 2-7:
DS39752B-page 8
High-Level Overview of the
Programming Process
Configuration Bits
Program Memory
Program Data EE
Configuration Bits
Verify Program
Perform Bulk
Program IDs
Verify Data
HIGH-LEVEL
PROGRAMMING FLOW
Verify IDs
Program
Erase
Verify
Done
Start
2.5
As shown in Figure 2-8, the High-Voltage ICSP
Program/Verify mode is entered by holding PGC and
PGD low, and then raising MCLR/V
V
ory, data EEPROM (see Section 3.3 “Data EEPROM
Programming”), ID locations and Configuration bits
can be accessed and programmed in serial fashion.
Figure 2-9 shows the exit sequence.
The sequence that enters the device into the Program/
Verify mode places all unused I/Os in the high-impedance
state.
FIGURE 2-8:
FIGURE 2-9:
IHH
MCLR/V
RA5/FLTA
V
PGD
PGC
MCLR/V
RA5/FLTA
V
PGD
PGC
(high voltage). Once in this mode, the code mem-
DD
DD
Entering and Exiting High-Voltage
ICSP Program/Verify Mode
PP
D110
PP
D110
/
/
ENTERING HIGH-VOLTAGE
PROGRAM/VERIFY MODE
EXITING HIGH-VOLTAGE
PROGRAM/VERIFY MODE
P13
PGD = Input
PGD = Input
P1
© 2009 Microchip Technology Inc.
P16
P1
P12
P17
PP
/RA5/FLTA to