PIC18F1220-I/SS Microchip Technology, PIC18F1220-I/SS Datasheet - Page 17

• Manufacturer Part Number: PIC18F1220-I/SS
• Description: IC MCU FLASH 2KX16 A/D 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1220-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 4KB (2K x 16)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7-ch x 10-bit
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOPAC164018 - MODULE SKT PROMATEII 20SSOP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.3
Data EEPROM is accessed one byte at a time via an
Address Pointer (register pair, EEADRH:EEADR) and
a Data Latch (EEDATA). Data EEPROM is written by
loading EEADRH:EEADR with the desired memory
location, EEDATA with the data to be written and initiat-
ing a memory write by appropriately configuring the
EECON1 register. A byte write automatically erases the
location and writes the new data (erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, both the EEPGD and CFGS bits must
be cleared (EECON1<7:6> = 00). The WREN bit must
be set (EECON1<2> = 1) to enable writes of any sort
and this must be done prior to initiating a write
sequence. The write sequence is initiated by setting the
WR bit (EECON1<1> = 1).
The write begins on the falling edge of the 4th PGC
after the WR bit is set. It ends when the WR bit is
cleared by hardware.
After the programming sequence terminates, PGC must
still be held low for the time specified by parameter P10
to allow high-voltage discharge of the memory array.
FIGURE 3-7:
© 2009 Microchip Technology Inc.
PGC
PGD
Poll WR bit
Data EEPROM Programming
4-Bit Command
1
0
2
0
3
0
4
0
PGC
PGD
P5
DATA EEPROM WRITE TIMING
BSF EECON1, WR
1
4-Bit Command
1
0
2
2
0
15 16
3
0
4
0
P5A
P5
MOVF EECON1, W, 0
1
2
15 16
PGD = Input
PGD = Input
P5A
4-Bit Command
1
0
Poll WR bit, Repeat until Clear
FIGURE 3-6:
2
0
3
0
(see below)
4
0
P11A
P5
PIC18F1230/1330
MOVWF TABLAT
1
2
No
15 16
PROGRAM DATA FLOW
Enable Write
Set Address
Start Write
Sequence
Set Data
WR bit
Done?
clear?
P5A
Done
Start
Yes
Yes
(see Figure 4-4)
Shift Out Data
PGD = Output
DS39752B-page 17
No
P10
16-Bit Data
Payload
1
n
2
n