PIC18F1220-I/SS Microchip Technology, PIC18F1220-I/SS Datasheet
PIC18F1220-I/SS
Specifications of PIC18F1220-I/SS
Related parts for PIC18F1220-I/SS
PIC18F1220-I/SS Summary of contents
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... SS RB6 PGC RB7 PGD Legend Input Output Power Note 1: All power supply (V ) and ground (V DD © 2009 Microchip Technology Inc. PIC18F1230/1330 2.1 Hardware Requirements In High-Voltage devices require two programmable power supplies: one for V DD supplies should have a minimum resolution of 0.25V. Refer to Section 6.0 “AC/DC Characteristics Timing Requirements for Program/Verify Test Mode” ...
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... RB2/INT2/KBI2/CMP2/T1OSO 3 16 RA7/OSC1/CLKI/T1OSI 4 15 RA6/OSC2/CLKO/T1OSO RB7/PWM5/PGD 7 12 RB6/PWM4/PGC 8 11 RB5/PWM3 9 10 RB4/PWM2 1 20 RB3/INT3/KBI3/CMP1/T1OSI 2 19 RB2/INT2/KBI2/CMP2/T1OSO + 3 18 RA7/OSC1/CLKI/T1OSI 4 17 RA6/OSC2/CLKO/T1OSO RB7/PWM5/PGD RB6/PWM4/PGC RB5/PWM3 10 11 RB4/PWM2 (1) (1) (1) (2) /FLTA (1) /AN3 /AV DD (1) (1) (1) (2) /FLTA (1) /AN3 DD DD © 2009 Microchip Technology Inc. ...
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... MCLR/V /RA5/FLTA RA2/TX/CK Note 1: Placement of T1OSI and T1OSO depends on the value of the Configuration bit, T1OSCMX of CONFIG3H. 2: Pin feature is dependent on device configuration. 3: Placement of FLTA depends on the value of the Configuration bit, FLTAMX of CONFIG3H. © 2009 Microchip Technology Inc. PIC18F1230/1330 21 RA7/OSC1/CLKI/T1OSI RA6/OSC2/CLKO/T1OSO PIC18F1X30 18 NC ...
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... Note 1: Placement of T1OSI and T1OSO depends on the value of the Configuration bit, T1OSCMX of CONFIG3H. 2: Pin feature is dependent on device configuration. 3: Placement of FLTA depends on the value of the Configuration bit, FLTAMX of CONFIG3H. DS39752B-page RA7/OSC1/CLKI/T1OSI 2 20 RA6/OSC2/CLKO/T1OSO PIC18F1330-ICD RB7/PWM5/PGD 15 RB6/PWM4/PGC 7 (1) (3) /FLTA (1) /AN3 DD © 2009 Microchip Technology Inc. ...
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... Note: Sizes of memory areas are not to scale. * Boot Block size is determined by the BBSIZ<1:0> bits in CONFIG4L. © 2009 Microchip Technology Inc. PIC18F1230/1330 The size of the Boot Block in PIC18F1230/1330 devices can be configured as 256, 512 or 1K words. This is done through the BBSIZ<1:0> bits in the Configuration register, CONFIG4L (see Table 5-1) ...
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... Sizes of memory areas are not to scale. * Boot Block size is determined by the BBSIZ<1:0> bits in CONFIG4L. DS39752B-page 6 MEMORY SIZE/DEVICE 8 Kbytes Address (PIC18F1330) Range 000000h Boot Block 0001FFh* or 0003FFh* or 0007FFh* 000200h* or 000400h or 000800h Block 0 000FFFh 001000h Block 1 001FFFh Unimplemented Read ‘0’s 01FFFFh © 2009 Microchip Technology Inc. ...
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... Configuration and ID Space 2FFFFFh 3FFFFFh Note: Sizes of memory areas are not to scale. © 2009 Microchip Technology Inc. PIC18F1230/1330 2.3.1 MEMORY ADDRESS POINTER Memory in the address space, 0000000h to 3FFFFFh, is addressed via the Table Pointer register, which is comprised of three pointer registers: • TBLPTRU at RAM address 0FF8h • ...
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... Verify mode places all unused I/Os in the high-impedance state. FIGURE 2-8: ENTERING HIGH-VOLTAGE PROGRAM/VERIFY MODE P13 P12 P1 D110 MCLR RA5/FLTA V DD PGD PGC PGD = Input FIGURE 2-9: EXITING HIGH-VOLTAGE PROGRAM/VERIFY MODE P16 P17 MCLR RA5/FLTA D110 V DD PGD PGC PGD = Input © 2009 Microchip Technology Inc. /RA5/FLTA to ...
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... PGC PGD 4-Bit Command © 2009 Microchip Technology Inc. PIC18F1230/1330 TABLE 2-3: Core Instruction (shift in16-bit instruction) Shift out TABLAT Register Table Read Table Read, Post-Increment Table Read, Post-Decrement Table Read, Pre-Increment Table Write Table Write, Post-Increment by 2 Table Write, Start Programming, ...
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... RA5/FLTA pin is ignored. During Programming Pin Type Dedicated Pin P ICRST/ICV Programming Enable PP I ICCK/ICPGC Serial Clock I/O ICDT/ICPGD Serial Data /RA5/FLTA pin prior to PP pin, then the state of PP pin is ignored. Likewise, when the PP prior to applying Pin Description © 2009 Microchip Technology Inc. / ...
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... P11). During this time, PGC may continue to toggle but PGD must be held low. © 2009 Microchip Technology Inc. PIC18F1230/1330 The code sequence to erase the entire device is shown in Table 3-2 and the flowchart is shown in Figure 3-1. ...
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... PIC18F1230/1330 device. The timing diagram that details the Start Programming command and parameters P9 and P10 is shown in Figure 3-5. Note: The TBLPTR register can point to any byte within the row intended for erase. P10 P11 Erase Time 16-Bit Data Payload © 2009 Microchip Technology Inc. ...
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... NOP – hold PGC high for time P9 and low for time P10. Step 4: Repeat step 3, with Address Pointer incremented by 64 until all rows are erased. FIGURE 3-3: SINGLE ROW ERASE CODE MEMORY FLOW Addr = Addr + 64 © 2009 Microchip Technology Inc. PIC18F1230/1330 Core Instruction EECON1, EEPGD EECON1, CFGS ...
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... MOVWF TBLPTRL Write 2 bytes and post-increment address by 2. Write 2 bytes and start programming. NOP - hold PGC high for time P9 and low for time P10. WRITE AND ERASE BUFFER SIZES Write Buffer Erase Buffer Size (bytes) Size (bytes © 2009 Microchip Technology Inc. ...
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... TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111 PGC P5 PGD 4-Bit Command 16-Bit Data Payload © 2009 Microchip Technology Inc. PIC18F1230/1330 Start LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at <Addr> All No bytes written? Yes Start Write Sequence and Hold PGC High until Done ...
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... MOVWF TBLPTRL Write 2 bytes and post-increment address by 2. Repeat as many times as necessary to fill the write buffer Write 2 bytes and start programming. NOP - hold PGC high for time P9 and low for time P10. BCF EECON1, WREN © 2009 Microchip Technology Inc. ...
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... PGC P5 PGD 4-Bit Command BSF EECON1 PGC Poll WR bit PGD 4-Bit Command © 2009 Microchip Technology Inc. PIC18F1230/1330 FIGURE 3-6: P5A P11A Poll WR bit, Repeat until Clear (see below) PGD = Input P5A 4-Bit Command MOVWF TABLAT MOVF EECON1 PGD = Input PROGRAM DATA FLOW ...
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... Core Instruction BCF EECON1, EEPGD BCF EECON1, CFGS MOVLW <Addr> MOVWF EEADR MOVLW <AddrH> MOVWF EEADRH MOVLW <Data> MOVWF EEDATA BSF EECON1, WREN BSF EECON1, WR MOVF EECON1 MOVWF TABLAT NOP (1) Shift out data BCF EECON1, WREN © 2009 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC18F1230/1330 Table 3-8 demonstrates the code sequence required to write the ID locations. In order to modify the ID locations, refer to the methodology described in Section 3.2.1 “Modifying Code Memory”. As with code memory, the ID locations must be erased before being modified ...
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... NOP - hold PGC high for time P9 and low for time P10. MOVLW 01h MOVWF TBLPTRL Load 2 bytes and start programming. NOP - hold PGC high for time P9 and low for time P10. Load Odd Configuration Address Program Delay P9 and P10 Time for Write Start MSB Done © 2009 Microchip Technology Inc. ...
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... PGD = Input © 2009 Microchip Technology Inc. PIC18F1230/1330 The 4-bit command is shifted in, LSb first. The read is executed during the next 8 clocks, then shifted out on PGD during the last 8 clocks, LSb to MSb. A delay of P6 must be introduced after the falling edge of the 8th PGC of the operand to allow PGD to transition from an input to an output ...
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... Pointer back to 00000h, rather than point to unimplemented address, 02000h. Set TBLPTR = 200000h Increment Pointer Failure, Report Error No Read Low Byte with Post-Increment Read High Byte with Post-Increment Does No Word = Expect Failure, Data? Report Error Yes All ID locations verified? Yes Done © 2009 Microchip Technology Inc. ...
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... Step 4: Load data into the Serial Data Holding register. 0000 50 A8 0000 6E F5 0000 00 00 0010 <MSB><LSB> Note 1: The <LSB> is undefined. The <MSB> is the data. © 2009 Microchip Technology Inc. PIC18F1230/1330 FIGURE 4-3: Core Instruction BCF EECON1, EEPGD BCF EECON1, CFGS MOVLW <Addr> MOVWF ...
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... Section 4.4 “Read Data EEPROM Memory” and Section 4.2 “Verify Code Memory and ID Locations” for implementation details. FIGURE 4-5: Start Blank Check Device device blank? Abort P5A 5 6 MSb Fetch Next 4-Bit Command PGD = Input BLANK CHECK FLOW Is Yes Continue No © 2009 Microchip Technology Inc. ...
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... Device PIC18F1230 PIC18F1330 PIC18F1330-ICD Note: The ‘x’s in DEVID1 contain the device revision code. © 2009 Microchip Technology Inc. PIC18F1230/1330 5.2 Device ID Word The Device ID Word for the PIC18F1230/1330 devices is located at 3FFFFEh:3FFFFFh. These bits may be used by the programmer to identify what device type is being programmed and read out normally, even after code or read protection ...
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... Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 © 2009 Microchip Technology Inc. ...
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... CP1 CONFIG5L Note 1: The BBSIZ<1:0> bits can not be changed once any of the following code-protect bits are enabled: CPB or CP0, WRTB or WRT0, EBTRB or EBTR0. © 2009 Microchip Technology Inc. PIC18F1230/1330 Description Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on SWDTEN bit) ...
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... Boot Block is protected from table reads executed in other blocks Device ID bits These bits are used with the DEV<2:0> bits in the DEVID1 register to identify the part number. Device ID bits These bits are used with the DEV<10:3> bits in the DEVID2 register to identify the part number. © 2009 Microchip Technology Inc. ...
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... EEPROM information must be included. An option to not include the data EEPROM information may be provided. When embedding data EEPROM information in the hex file, it should start at address F00000h. Microchip Technology Inc. believes that this feature is important for the benefit of the end customer. © 2009 Microchip Technology Inc. PIC18F1230/1330 5 ...
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... Description CFGW = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Byte-wise sum of lower four bits of all customer ID locations + = Addition & = Bit-wise AND DS39752B-page 30 Checksum © 2009 Microchip Technology Inc. 0xAA at 0 Blank and Max Value Address F33E F294 F521 F4C7 F732 F6D8 ...
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... Legend: Item Description CFGW = Configuration Word SUM[a:b] = Sum of locations inclusive SUM_ID = Byte-wise sum of lower four bits of all customer ID locations + = Addition & = Bit-wise AND © 2009 Microchip Technology Inc. PIC18F1230/1330 Checksum 0xAA at 0 Blank and Max Value Address E33E E294 E520 E4C6 ...
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... V (Note 2) V Externally timed, row erases and all writes V Self-timed, bulk erases only (Note 3) μA (Note meet AC specifications μs (Notes 5.0V DD μ Externally Timed μ the oscillator period. For OSC © 2009 Microchip Technology Inc. ...
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... T is the instruction cycle time specific values, refer to the Electrical Characteristics section of the device data sheet for the particular device. 2: This specification also applies to ICV 3: At 0°C-50°C. © 2009 Microchip Technology Inc. PIC18F1230/1330 Min Max 4 — /RA5/FLTA ↑ 2 — ...
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... PIC18F1230/1330 NOTES: DS39752B-page 34 © 2009 Microchip Technology Inc. ...
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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2009 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...