PIC18F1220-I/SS Microchip Technology, PIC18F1220-I/SS Datasheet - Page 12

• Manufacturer Part Number: PIC18F1220-I/SS
• Description: IC MCU FLASH 2KX16 A/D 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1220-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 4KB (2K x 16)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7-ch x 10-bit
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOPAC164018 - MODULE SKT PROMATEII 20SSOP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F1230/1330
FIGURE 3-2:
3.1.2
For a PIC18F1230/1330 device, it is possible to erase
one row (64 bytes of data), provided the block is not
code or write-protected. Rows are located at static
boundaries, beginning at program memory address
000000h, extending to the internal program memory
limit (see Section 2.3 “Memory Maps”).
The Row Erase duration is externally timed and is
controlled by PGC. After the WR bit in EECON1 is set,
a NOP is issued, where the 4th PGC is held high for the
duration of the programming time, P9.
DS39752B-page 12
PGC
PGD
4-Bit Command
1
0
ICSP ROW ERASE
2
0
3
1
4
1
P5
BULK ERASE TIMING
1
1
Data Payload
2
1
16-Bit
15 16
0
0
P5A
4-Bit Command
1
0
2
0
3
0
4
0
PGD = Input
P5
1
0
Data Payload
2
0
16-Bit
After PGC is brought low, the programming sequence
is terminated. PGC must be held low for the time
specified by parameter P10 to allow high-voltage
discharge of the memory array.
The code sequence to Row Erase a PIC18F1230/1330
device is shown in Table 3-3. The flowchart shown in
Figure 3-3 depicts the logic necessary to completely
erase a PIC18F1230/1330 device. The timing diagram
that details the Start Programming command and
parameters P9 and P10 is shown in Figure 3-5.
15 16
Note:
0
0
P5A
4-Bit Command
1
0
The TBLPTR register can point to any byte
within the row intended for erase.
2
0
3
0
4
0
© 2009 Microchip Technology Inc.
Erase Time
P11
P10
Data Payload
1
16-Bit
n
2
n