ATA6612P-PLPW Atmel, ATA6612P-PLPW Datasheet - Page 61
![MCU W/LIN TXRX REG WTCHDG 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
ATA6612P-PLPW
Manufacturer Part Number
ATA6612P-PLPW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6612-EK.pdf
(364 pages)
Specifications of ATA6612P-PLPW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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6.6.11.1
9111H–AUTO–01/11
Clock Prescale Register – CLKPR
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
Interrupts must be disabled when changing prescaler setting to make sure the write procedure
is not interrupted.
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0
Initial Value
Read/Write
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The
CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to
zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits
are written. Rewriting the CLKPCE bit within this time-out period does neither extend the
time-out period, nor clear the CLKPCE bit.
These bits define the division factor between the selected clock source and the internal
system clock. These bits can be written run-time to vary the clock frequency to suit the
application requirements. As the divider divides the master clock input to the MCU, the
speed of all synchronous peripherals is reduced when a division factor is used. The divi-
sion factors are given in
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unpro-
grammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits
are reset to “0011”, giving a division factor of 8 at start up. This feature should be used if
the selected clock source has a higher frequency than the maximum frequency of the
device at the present operating conditions. Note that any value can be written to the
CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure
that a sufficient division factor is chosen if the selected clock source has a higher fre-
quency than the maximum frequency of the device at the present operating conditions.
The device is shipped with the CKDIV8 Fuse programmed.
Bit
CLKPR to zero.
CLKPCE
R/W
7
0
R
6
–
0
Table 6-17 on page
R
5
–
0
R
4
–
0
Atmel ATA6612/ATA6613
62.
CLKPS3 CLKPS2 CLKPS1 CLKPS0
R/W
3
See Bit Description
R/W
2
R/W
1
R/W
0
CLKPR
61
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