ATA6612P-PLPW Atmel, ATA6612P-PLPW Datasheet - Page 185
![MCU W/LIN TXRX REG WTCHDG 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
ATA6612P-PLPW
Manufacturer Part Number
ATA6612P-PLPW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6612-EK.pdf
(364 pages)
Specifications of ATA6612P-PLPW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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9111H–AUTO–01/11
The interconnection between Master and Slave CPUs with SPI is shown in
system consists of two shift Registers, and a Master clock generator. The SPI Master initiates
the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Mas-
ter and Slave prepare the data to be sent in their respective shift Registers, and the Master
generates the required clock pulses on the SCK line to interchange data. Data is always
shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Mas-
ter on the Master In – Slave Out, MISO, line. After each data packet, the Master will
synchronize the Slave by pulling high the Slave Select, SS, line.
When configured as a Master, the SPI interface has no automatic control of the SS line. This
must be handled by user software before communication can start. When this is done, writing
a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the
eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end
of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set,
an interrupt is requested. The Master may continue to shift the next byte by writing it into
SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming
byte will be kept in the Buffer Register for later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as
long as the SS pin is driven high. In this state, software may update the contents of the SPI
Data Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK
pin until the SS pin is driven low. As one byte has been completely shifted, the end of Trans-
mission Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an
interrupt is requested. The Slave may continue to place new data to be sent into SPDR before
reading the incoming data. The last incoming byte will be kept in the Buffer Register for later
use.
Figure 6-66. SPI Master-slave Interconnection
The system is single buffered in the transmit direction and double buffered in the receive direc-
tion. This means that bytes to be transmitted cannot be written to the SPI Data Register before
the entire shift cycle is completed. When receiving data, however, a received character must
be read from the SPI Data Register before the next character has been completely shifted in.
Otherwise, the first byte is lost.
CLOCK GENERATOR
SPI
MSB
8 BIT SHIFT REGISTER
MASTER
LSB
Atmel ATA6612/ATA6613
MISO MISO
MOSI MOSI
SS
SCK
SCK
SS
MSB
8 BIT SHIFT REGISTER
SLAVE
Figure
SHIFT
ENABLE
LSB
6-66. The
185
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