ATA6612P-PLPW Atmel, ATA6612P-PLPW Datasheet - Page 260
![MCU W/LIN TXRX REG WTCHDG 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
ATA6612P-PLPW
Manufacturer Part Number
ATA6612P-PLPW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6612-EK.pdf
(364 pages)
Specifications of ATA6612P-PLPW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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6.19.8.6
Figure 6-96. Combining Several TWI Modes to Access a Serial EEPROM
6.19.9
260
Atmel ATA6612/ATA6613
Multi-master Systems and Arbitration
S
S = START
Combining Several TWI Modes
Transmitted from master to slave
SLA+W
In some cases, several TWI modes must be combined in order to complete the desired action.
Consider for example reading data from a serial EEPROM. Typically, such a transfer involves
the following steps:
Note that data is transmitted both from Master to Slave and vice versa. The Master must
instruct the Slave what location it wants to read, requiring the use of the MT mode. Subse-
quently, data must be read from the Slave, implying the use of the MR mode. Thus, the
transfer direction must be changed. The Master must keep control of the bus during all these
steps, and the steps should be carried out as an atomical operation. If this principle is violated
in a multi master system, another Master can alter the data pointer in the EEPROM between
steps 2 and 3, and the Master will read the wrong data location. Such a change in transfer
direction is accomplished by transmitting a REPEATED START between the transmission of
the address byte and reception of the data. After a REPEATED START, the Master keeps
ownership of the bus. The following figure shows the flow in this transfer.
If multiple masters are connected to the same bus, transmissions may be initiated simultane-
ously by one or more of them. The TWI standard ensures that such situations are handled in
such a way that one of the masters will be allowed to proceed with the transfer, and that no
data will be lost in the process. An example of an arbitration situation is depicted below, where
two masters are trying to transmit data to a Slave Receiver.
1. The transfer must be initiated.
2. The EEPROM must be instructed what location should be read.
3. The reading must be performed.
4. The transfer must be finished.
A
Master Transmitter
ADDRESS
A
Rs = REPEATED START
Rs
Transmitted from slave to master
SLA+R
A
Master Receiver
DATA
P = STOP
A
9111H–AUTO–01/11
P
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