ATA6616-P3QW Atmel, ATA6616-P3QW Datasheet - Page 217
ATA6616-P3QW
Manufacturer Part Number
ATA6616-P3QW
Description
TXRX MULTICHIP MOD LIN SIP 38QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6617-EK.pdf
(308 pages)
Specifications of ATA6616-P3QW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
38-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA6616-P3QW
Manufacturer:
ATMEL
Quantity:
950
Part Number:
ATA6616-P3QW
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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4.18.4
9132D–AUTO–12/10
Starting a Conversion
A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.
This bit stays high as long as the conversion is in progress and will be cleared by hardware
when the conversion is completed. If a different data channel is selected while a conversion is
in progress, the ADC will finish the current conversion before performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering
is enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA register. The trig-
ger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB register (see
description of the ADTS bits for a list of the trigger sources). When a positive edge occurs on
the selected trigger signal, the ADC prescaler is reset and a conversion is started. This pro-
vides a method of starting conversions at fixed intervals. If the trigger signal still is set when
the conversion completes, a new conversion will not be started. If another positive edge
occurs on the trigger signal during conversion, the edge will be ignored. Note that an Interrupt
Flag will be set even if the specific interrupt is disabled or the Global Interrupt Enable bit in
SREG register is cleared. A conversion can thus be triggered without causing an interrupt.
However, the Interrupt Flag must be cleared in order to trigger a new conversion at the next
interrupt event.
Figure 4-83. ADC Auto Trigger Logic
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as
soon as the ongoing conversion has finished. The ADC then operates in Free Running mode,
constantly sampling and updating the ADC Data Register. The first conversion must be started
by writing a logical one to the ADSC bit in ADCSRA register. In this mode the ADC will perform
successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or
not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA
register to one. ADSC can also be used to determine if a conversion is in progress. The ADSC
bit will be read as one during a conversion, independently of how the conversion was started.
SOURCE 1
SOURCE n
. . .
. . .
. . .
. . .
ADSC
ADIF
ADTS[2:0]
Detector
Edge
ADATE
Atmel ATA6616/ATA6617
Start
ADC Prescaler
Conversion
CLK
Logic
CLK
IO
ADC
217
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