ATA6616-P3QW Atmel, ATA6616-P3QW Datasheet - Page 115

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ATA6616-P3QW

Manufacturer Part Number
ATA6616-P3QW
Description
TXRX MULTICHIP MOD LIN SIP 38QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet

Specifications of ATA6616-P3QW

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
38-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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4.11.6.1
4.11.6.2
9132D–AUTO–12/10
Compare Output Function
Compare Output Mode and Waveform Generation
Figure 4-33. Compare Match Output Logic
The general I/O port function is overridden by the Output Compare (OC0A) from the Wave-
form Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction (input
or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data
Direction Register bit for the OC0A pin (DDR_OC0A) must be set as output before the OC0A
value is visible on the pin. The port override function is independent of the Waveform Genera-
tion mode.
The design of the Output Compare pin logic allows initialization of the OC0A state before the
output is enabled. Note that some COM0A1:0 bit settings are reserved for certain modes of
operation.
The Waveform Generator uses the COM0A1:0 bits differently in normal, CTC, and PWM
modes. For all modes, setting the COM0A1:0 = 0 tells the Waveform Generator that no action
on the OC0A Register is to be performed on the next compare match. For compare output
actions in the non-PWM modes refer to
Table 4-31 on page
A change of the COM0A1:0 bits state will have effect at the first compare match after the bits
are written. For non-PWM modes, the action can be forced to have immediate effect by using
the FOC0A strobe bits.
See ”8-bit Timer/Counter Register Description” on page 124.
COMnx1
COMnx0
FOCnx
clk
I/O
124, and for phase correct PWM refer to
Waveform
Generator
Table 4-30 on page
D
D
D
PORT
OCnx
DDR
Atmel ATA6616/ATA6617
Q
Q
Q
1
0
124. For fast PWM mode, refer to
Table 4-32 on page
OCnx
Pin
125.
115

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