ATA6616-P3QW Atmel, ATA6616-P3QW Datasheet - Page 152
ATA6616-P3QW
Manufacturer Part Number
ATA6616-P3QW
Description
TXRX MULTICHIP MOD LIN SIP 38QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6617-EK.pdf
(308 pages)
Specifications of ATA6616-P3QW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
38-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA6616-P3QW
Manufacturer:
ATMEL
Quantity:
950
Part Number:
ATA6616-P3QW
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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Atmel ATA6616/ATA6617
Figure 4-52. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM.
When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 flag is set
accordingly at the same timer clock cycle as the OCR1A/B Registers are updated with the
double buffer value (at TOP). The interrupt flags can be used to generate an interrupt each
time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNT1 and the
OCR1A/B. Note that when using fixed TOP values, the unused bits are masked to zero when
any of the OCR1A/B Registers are written. As the third period shown in
changing the TOP actively while the Timer/Counter is running in the phase correct mode can
result in an unsymmetrical output. The reason for this can be found in the time of update of the
OCR1A/B Register. Since the OCR1A/B update occurs at TOP, the PWM period starts and
ends at TOP. This implies that the length of the falling slope is determined by the previous
TOP value, while the length of the rising slope is determined by the new TOP value. When
these two values differ the two slopes of the period will differ in length. The difference in length
gives the unsymmetrical result on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct
mode when changing the TOP value while the Timer/Counter is running. When using a static
TOP value there are practically no differences between the two modes of operation.
TCNTn
OCnxi
OCnxi
Period
1
2
3
4
Figure 4-52
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TOVn Interrupt Flag Set
(Interrupt on Bottom)
9132D–AUTO–12/10
(COMnx1:0 = 2)
(COMnx1:0 = 3)
illustrates,
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