ATMEGA16U2-AUR Atmel, ATMEGA16U2-AUR Datasheet - Page 68
![MCU AVR 8K FLASH 16MHZ 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATMEGA16U2-AUR
Manufacturer Part Number
ATMEGA16U2-AUR
Description
MCU AVR 8K FLASH 16MHZ 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA16U2-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
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12.2
12.2.1
7799D–AVR–11/10
Ports as General Digital I/O
Configuring the Pin
Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the port as general digital I/O.
The ports are bi-directional I/O ports with optional internal pull-ups.
tional description of one I/O-port pin, here generically called Pxn.
Figure 12-2. General Digital I/O
Note:
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in
Description for I/O-Ports” on page
PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to
be configured as an output pin. The port pins are tri-stated when reset condition becomes active,
even if no clocks are running.
Pxn
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
SLEEP, and PUD are common to all ports.
PUD:
SLEEP:
clk
I/O
:
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
SLEEP
(1)
82, the DDxn bits are accessed at the DDRx I/O address, the
SYNCHRONIZER
D
L
Q
Q
D
PINxn
ATmega8U2/16U2/32U2
Q
Q
RESET
RESET
PORTxn
WDx:
RDx:
WRx:
RRx:
RPx:
WPx:
Q
Q
Q
Q
DDxn
CLR
CLR
D
D
RRx
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx REGISTER
PUD
WDx
RDx
RPx
clk
1
0
Figure 12-2
I/O
WRx
WPx
shows a func-
“Register
I/O
,
68
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