AT89LP214-20XU Atmel, AT89LP214-20XU Datasheet - Page 59
![MCU 8051 2K FLASH 20MHZ 14-TSSOP](/photos/12/32/123207/14x-tssop_sml.jpg)
AT89LP214-20XU
Manufacturer Part Number
AT89LP214-20XU
Description
MCU 8051 2K FLASH 20MHZ 14-TSSOP
Manufacturer
Atmel
Series
89LPr
Datasheet
1.AT89LP213-20PU.pdf
(98 pages)
Specifications of AT89LP214-20XU
Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
14-TSSOP
Package
14TSSOP
Device Core
8051
Family Name
AT89
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
12
Interface Type
SPI/UART
Number Of Timers
2
Core
8051
Processor Series
AT89x
Maximum Clock Frequency
20 MHz
Data Ram Size
128 B
Mounting Style
SMD/SMT
Height
1.05 mm
Length
5.1 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.4 V
Width
4.5 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
20.1
Table 20-2.
Table 20-3.
3538E–MICRO–11/10
WDTCON Address = A7H
Not Bit Addressable
Bit
Symbol
PS2
PS1
PS0
WDIDLE
SWRST
WDTOVF
WDTEN
WDTCON Address = A6H
Not Bit Addressable
Bit
The WDT is enabled by writing the sequence 1EH/E1H to the WDTRST SFR. The current status may be checked by reading
the WDTEN bit in WDTCON. To prevent the WDT from resetting the device, the same sequence 1EH/E1H must be written to
WDTRST before the time-out interval expires. A software reset is generated by writing the sequence 5AH/A5H to WDTRST.
Software Reset
PS2
7
–
7
Function
Prescaler bits for the watchdog timer (WDT). When all three bits are cleared to 0, the watchdog timer has a nominal
period of 16K clock cycles. When all three bits are set to 1, the nominal period is 2048K clock cycles.
Disable/enable the Watchdog Timer in IDLE mode. When WDIDLE = 0, WDT continues to count in IDLE mode. When
WDIDLE = 1, WDT freezes while the device is in IDLE mode.
Software Reset Flag. Set when a software reset is generated by writing the sequence 5AH/A5H to WDTRST. Also set
when an incorrect sequence is written to WDTRST. Must be cleared by software.
Watchdog Overflow Flag. Set when a WDT rest is generated by the WDT timer overflow. Also set when an incorrect
sequence is written to WDTRST. Must be cleared by software.
Watchdog Enable Flag. This bit is READ-ONLY and reflects the status of the WDT (whether it is running or not). The
WDT is disabled after any reset and must be re-enabled by writing 1EH/E1H to WDTRST
WDTCON – Watchdog Control Register
WDTRST – Watchdog Reset Register
PS1
–
6
6
A Software Reset of the AT89LP213/214 is accomplished by writing the software reset
sequence 5AH/A5H to the WDTRST SFR. The WDT does not need to be enabled to generate
the software reset. A normal software reset will set the SWRST flag in WDTCON. However, if at
any time an incorrect sequence is written to WDTRST (i.e. anything other than 1EH/E1H or
5AH/A5H), a software reset will immediately be generated and both the SWRST and WDTOVF
flags will be set. In this manner an intentional software reset may be distinguished from a soft-
ware error-generated reset. The program sequence to generate a software reset is as follows:
PS0
–
5
5
MOV WDTRST, #05Ah
MOV WDTRST, #0A5h
WDIDLE
4
–
4
–
–
3
3
SWRST
–
2
2
Reset Value = 0000 X000B
WDTOVF
AT89LP213/214
1
–
1
(Write-Only)
WDTEN
0
–
0
59