M30624FGAFP#U5 Renesas Electronics America, M30624FGAFP#U5 Datasheet - Page 155
![IC M16C MCU FLASH 100QFP](/photos/12/31/123149/m30624fgafp_u5_sml.jpg)
M30624FGAFP#U5
Manufacturer Part Number
M30624FGAFP#U5
Description
IC M16C MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.M30622SAFPU5.pdf
(277 pages)
2.M30622SAFPU5.pdf
(617 pages)
3.M30622SAFPU5.pdf
(308 pages)
4.M30624FGAFPU5.pdf
(275 pages)
Specifications of M30624FGAFP#U5
Core Processor
M16C/60
Core Size
16-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
Cpu Family
M16C
Device Core Size
16/32Bit
Frequency (max)
16MHz
Interface Type
SIM/UART
Total Internal Ram Size
20KB
# I/os (max)
87
Number Of Timers - General Purpose
11
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.2V
On-chip Adc
10-chx10-bit
On-chip Dac
2-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-20C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
PQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30624FGAFP#U5M30624FGAFP#D3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30624FGAFP#U5M30624FGAFP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- M30622SAFPU5 PDF datasheet
- M30622SAFPU5 PDF datasheet #2
- M30622SAFPU5 PDF datasheet #3
- M30624FGAFPU5 PDF datasheet #4
- Current page: 155 of 617
- Download datasheet (9Mb)
Clock asynchronous serial I/O (UART) mode
1-134
Figure 1.16.22. Typical transmit/receive timing in UART mode (used for the SIM interface)
Note 1: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
TxD
RxD
Transmit register
empty flag (TXEPT)
RxD
TxD
Signal conductor level
(Note 2)
Receive complete
flag (RI)
Transfer clock
Transmit enable
bit(TE)
Transmit buffer
empty flag(TI)
Signal conductor level
(Note 2)
Transmit interrupt
request bit (IR)
Transfer clock
Receive enable
bit (RE)
Receive interrupt
request bit (IR)
Note 2: Equal in waveform because TxD
2
2
2
2
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
The above timing applies to the following settings :
Shown in ( ) are bit symbols.
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
“1”
“0”
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “0”.
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
Start
ST
ST
Start
ST
ST
bit
bit
D
D
D
D
0
0
0
0
Data is set in UART2 transmit buffer register
D
D
D
D
1
1
1
1
Tc
2
Tc
D
D
D
D
and RxD
2
2
2
2
D
D
D
D
3
3
3
3
D
D
D
D
4
4
4
4
2
D
D
D
D
are connected.
5
5
5
5
D
D
Transferred from UART2 transmit buffer register to UART2 transmit register
D
D
6
6
6
6
D
D
D
Parity
D
Parity
7
7
7
7
bit
bit
Tc = 16 (n + 1) / fi
Tc = 16 (n + 1) / fi
P
P
P
P
Cleared to “0” when interrupt request is accepted, or cleared by software
SP
Cleared to “0” when interrupt request is accepted, or cleared by software
SP
SP
SP
fi : frequency of BRG2 count source (f
n : value set to BRG2
fi : frequency of BRG2 count source (f
n : value set to BRG2
Stop
Stop
bit
bit
Read to receive buffer
ST
ST
ST
The level is detected by the
interrupt routine.
ST
Note 1
An “L” level returns from TxD
the occurrence of a parity error.
An “L” level returns from TxD
the occurrence of a parity error.
D
D
D
D
0
0
0
0
D
D
D
D
1
1
1
1
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D
D
D
D
2
2
2
2
D
D
D
D
3
3
3
3
D
D
D
D
4
4
4
4
D
D
1
D
D
1
, f
5
5
, f
5
5
2
8
8
D
D
2
, f
due to
D
, f
D
6
6
due to
6
6
32
32
D
D
D
)
)
D
7
7
7
7
P
P
P
P
Read to receive buffer
M16C / 62A Group
SP
SP
Mitsubishi microcomputers
SP
SP
The level is
detected by the
interrupt routine.
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