DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 958
DF2505BR26DV
Manufacturer Part Number
DF2505BR26DV
Description
IC H8S/2505 MCU FLASH 176-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Specifications of DF2505BR26DV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2505BR26DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Appendix
Legend:
H:
L:
T:
Keep: Input port becomes high-impedance, output port retains state
DDR:
OPE:
WAITE: Wait input enable
BRLE: Bus release enable
Notes: 1. PG3 and PG2 are not supported in the H8S/2556 Group.
Rev. 6.00 Sep. 24, 2009 Page 910 of 928
REJ09B0099-0600
Port Name
Pin Name
PG4/CS0
PG3/RX/CS1*
PG2/TX/CS2*
PG1/CS3/IRQ7
PG0/IRQ6
Port H
Port J
THxD*
HRxD*
2
2
High level
Low level
High-impedance
Data direction register
Output port enable
2. Supported only in the H8S/2556 Group.
3. Output pins are in the high-impedance state when the power is supplied.
1
PG3/RX/CS1 and PG2/TX/CS2 are supported in the H8S/2552 Group. (When IEE bit is
1, RX and TX are valid.)
PG3/CS1 and PG2/CS2 are supported in the H8S/2506 Group.
1
MCU
Operating
Mode
6
7
6
7
6, 7
6, 7
6, 7
6, 7
6, 7
Power-On
Reset
T
T
T
T
T
T
T
H*
Input
3
Input
Manual
Reset
keep
keep
keep
keep
keep
keep
keep
H
Hardware
Standby
Mode
T
T
T
T
T
T
T
T
T
Software Standby
Mode,
Watch Mode
[DDR • OPE = 0]
T
[DDR • OPE = 1]
H
keep
[DDR • OPE = 0]
T
[DDR • OPE = 1]
H
keep
keep
keep
keep
H
T
Bus Release
State
T
keep
T
keep
keep
keep
Input
keep
keep
HRxD Input
Program
Execution
State,
Sleep Mode
[DDR = 0]
Input port
[DDR = 1]
CS0
(H in sleep
mode)
I/O port
[DDR = 0]
Input port
[DDR = 1]
CS1 to CS3
I/O port
I/O port
I/O port
I/O port
THxD Output
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