DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 160

• Manufacturer Part Number: DF2505BR26DV
• Description: IC H8S/2505 MCU FLASH 176-LFBGA
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505BR26DV

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 176-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 5 Interrupt Controller
Operation Order: When the same interrupts are selected as DTC activation source and CPU
interruption source, DTC data is transferred, and then CPU interrupt exception processing is made.
Table 5.9 shows interrupt source selection and interrupt source clear control by the setting of the
DTCE bit in DTCERA to DTCERG, and DTCERI of the DTC and the setting of the DISEL bit in
MRB of the DTC.
Table 5.9
Legend:
#:
O :
X:
*:
Usage Note: Interrupt sources of the SCI and A/D converter are cleared when the DTC reads or
writes prescribed register, and they do not depend on the DTCE or DISEL bit.
5.6
5.6.1
When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes
effective after execution of the instruction.
When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an
interrupt is generated during execution of the instruction, the interrupt concerned will still be
enabled on completion of the instruction, and so interrupt exception handling for that interrupt will
be executed on completion of the instruction. However, if there is an interrupt request of higher
priority than that interrupt, interrupt exception handling will be executed for the higher-priority
interrupt, and the lower-priority interrupt will be ignored.
Rev. 6.00 Sep. 24, 2009 Page 112 of 928
REJ09B0099-0600
Settings
DTC
DTCE
0
1
Corresponding interrupt is used. Interrupt source is cleared.
(The CPU should clear the source flag in the interrupt processing routine.)
Corresponding interrupt is used. Interrupt source is not cleared.
Corresponding interrupt cannot be used.
Don’t care
Usage Notes
Contention between Interrupt Generation and Disabling
Interrupt Source Selection and Clear Control
DESEL
∗
0
1
Interrupt Source Selection and Clear
Control
DTC
X
#
O
CPU
#
X
#