DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 141
DF2505BR26DV
Manufacturer Part Number
DF2505BR26DV
Description
IC H8S/2505 MCU FLASH 176-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Specifications of DF2505BR26DV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2505BR26DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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5.3.4
ISR indicates the status of IRQ7 to IRQ 0 interrupt requests.
Note:
Bit
1
0
Bit
7
6
5
4
3
2
1
0
*
Bit Name
IRQ0SCB
IRQ0SCA
Bit Name
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
IRQ Status Register (ISR)
Only 0 can be written to this bit to clear the flag.
Initial
Value
0
0
Initial
Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
IRQ0 Sense Control B
IRQ0 Sense Control A
00: Interrupt request is generated at IRQ0 input level low
01: Interrupt request is generated at falling edge of IRQ0
10: Interrupt request is generated at rising edge of IRQ0
11: Interrupt request is generated at both falling and rising
Description
IRQ7 to IRQ0 flags
These bits indicate the status of IRQ7 to IRQ0 interrupt
requests.
[Setting condition]
•
[Clearing conditions]
•
•
•
•
input
input
edges of IRQ0 input
When the interrupt source selected by the ISCR
registers occurs
Cleared by reading IRQnF flag when IRQnF = 1, then
writing 0 to IRQnF flag
When interrupt exception handling is executed while
low-level detection is set and IRQn (n = 0 to 7) input
is high
When IRQn interrupt exception handling is executed
while detection of falling edge, rising edge, or both
edges is set
When the DTC is activated by an IRQn interrupt, and
the DISEL bit in MRB of the DTC with the transfer
counter other than 0 is cleared to 0
Rev. 6.00 Sep. 24, 2009 Page 93 of 928
Section 5 Interrupt Controller
REJ09B0099-0600
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