DF2505BR26DV Renesas Electronics America, DF2505BR26DV Datasheet - Page 534
DF2505BR26DV
Manufacturer Part Number
DF2505BR26DV
Description
IC H8S/2505 MCU FLASH 176-LFBGA
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Specifications of DF2505BR26DV
Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
176-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
DF2505BR26DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 14 I
14.3.4
ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be
transferred, and confirms acknowledge bits to be received.
Rev. 6.00 Sep. 24, 2009 Page 486 of 928
REJ09B0099-0600
Bit
7
6
5
Bit Name
TIE
TEIE
RIE
I
2
C Bus Interrupt Enable Register (ICIER)
2
C Bus Interface 2 (IIC2)
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
Transmit Interrupt Enable
When the TDRE bit in ICSR is set to 1, this bit enables or
disables the transmit data empty interrupt (TXI).
0: Transmit data empty interrupt request (TXI) is disabled.
1: Transmit data empty interrupt request (TXI) is enabled.
Transmit End Interrupt Enable
This bit enables or disables the transmit end interrupt (TEI)
at the rising of the ninth clock while the TDRE bit in ICSR
is 1. TEI can be canceled by clearing the TEND bit or the
TEIE bit to 0.
0: Transmit end interrupt request (TEI) is disabled.
1: Transmit end interrupt request (TEI) is enabled.
Receive Interrupt Enable
This bit enables or disables the receive data full interrupt
request (RXI) and the overrun error interrupt request (ERI)
with the clocked synchronous format, when a receive data
is transferred from ICDRS to ICDRR and the RDRF bit in
ICSR is set to 1. RXI can be canceled by clearing the
RDRF or RIE bit to 0.
0: Receive data full interrupt request (RXI) and overrun
1: Receive data full interrupt request (RXI) and overrun
error interrupt request (ERI) with the clocked
synchronous format are disabled.
error interrupt request (ERI) with the clocked
synchronous format are enabled.
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