DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 57

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

2.4.2
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched for read, the least significant PC bit is regarded as 0.)
2.4.3
EXR is an 8-bit register that can be operated by the LDC, STC, ANDC, ORC, and XORC
instructions. When an instruction other than STC is executed, all interrupts including NMI are
masked in three states after the instruction is completed.
Bit
7
6 to3
2 to 0
Bit Name
T

I2
I1
I0
Program Counter (PC)
Extended Control Register (EXR)
Initial
Value
0
All1
1
1
1
SP (ER7)
R/W
R/W

R/W
R/W
R/W
Figure 2.8 Stack
Description
Trace Bit
When this bit is set to 1, trace exception processing
starts every when an instruction is executed. When
this bit is cleared to 0, instructions are consecutively
executed.
Reserved
These bits are always read as 1.
Interrupt Mask Bits 2 to 0
Specify interrupt request mask levels (0 to 7). In this
LSI, these bits cannot be used as the interrupt mask
level.
Rev. 2.00, 03/04, page 23 of 534
Stack area
Free area