DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 329

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

11.3.6
SCR performs enabling or disabling of SCI transfer operations and interrupt requests, and
selection of the transfer/receive clock source. For details on interrupt requests, refer to section
11.5, Interrupt Sources.
Bit
1
0
Bit
7
6
Bit Name
CKS1
CKS0
Bit Name
TIE
RIE
Serial Control Register (SCR)
Initial
Value
0
0
Initial
Value
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Clock Select 1 and 0
These bits select the clock source for the on-chip baud
rate generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relation between the bit rate register setting and
the baud rate, see section 11.3.8, Bit Rate Register
(BRR). n is the decimal display of the value of n in BRR
(see section 11.3.8, Bit Rate Register (BRR)).
Transmit Interrupt Enable
Receive Interrupt Enable
Description
Description
When this bit is set to 1, TXI interrupt request is
enabled.
TXI interrupt request cancellation can be performed by
reading 1 from the TDRE flag, then clearing it to 0, or
clearing the TIE bit to 0.
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
RXI and ERI interrupt request cancellation can be
performed by reading 1 from the RDRF flag, or the
FER, PER, or ORER flag, then clearing the flag to 0, or
by clearing the RIE bit to 0.
Rev. 2.00, 03/04, page 295 of 534