DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 219

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

which the DA bit is set to 1. When changing register settings after a 0-write to the DA bit, it is
necessary to confirm that the DA bit has been cleared to 0. Figure 7.12 shows the procedure for
changing register settings in an operating channel.
BEF Bit in DMMDR: In block transfer mode, the specified number of transfers (equivalent to the
block size) is performed in response to a single transfer request. To ensure that the correct number
of transfers is carried out, a block-size transfer is always executed, except in the event of a reset,
transition to standby mode, or generation of an NMI interrupt.
If an NMI interrupt is generated during block transfer, operation is halted midway through a
block-size transfer and the DA bit is cleared to 0, terminating the transfer operation. In this case
the BEF bit, which indicates the occurrence of an error during block transfer, is set to 1.
IRF Bit in DMMDR: The IRF bit in DMMDR is set to 1 when an interrupt request source occurs.
If the DIE bit in DMMDR is 1 at this time, an interrupt is requested. The timing for setting the IRF
bit to 1 is when the DA bit in DMMDR is cleared to 0 and transfer ends following the end of the
DMA transfer bus cycle in which the source generating the interrupt occurred.
If the DA bit is set to 1 and transfer is resumed during interrupt handling, the IRF bit is
automatically cleared to 0 and the interrupt request is cleared. For details on interrupts, see section
7.5, Interrupt Sources.
Changing register settings
Figure 7.12 Procedure for Changing Register Settings in Operating Channel
Change register settings
changes completed
in operating channel
Write 0 to DA bit
Register setting
Read DA bit
DA bit = 0?
Yes
No
1
2
3
4
1. Write 0 to the DA bit in DMMDR.
2. Read the DA bit.
3. Confirm that DA = 0. If DA = 1, this
4. Write the required set values to the
indicates that DMA transfer is in progress.
registers.
Rev. 2.00, 03/04, page 185 of 534