DF2170BVTE33V Renesas Electronics America, DF2170BVTE33V Datasheet - Page 511

• Manufacturer Part Number: DF2170BVTE33V
• Description: IC H8S/2170 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2170BVTE33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: SCI, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Clearing Hardware Standby Mode: Hardware standby mode is cleared by means of the STBY
pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is
set and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillator
stabilizes (for details on the oscillation stabilization time, refer to table 16.2). When the RES pin is
subsequently driven high, a transition is made to the program execution state via the reset
exception handling state.
Hardware Standby Mode Timing: Figure 16.3 shows an example of hardware standby mode
timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is
made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin
high, waiting for the oscillation stabilization time, then changing the RES pin from low to high.
Oscillator
Oscillation
Reset
stabilization
exception
time
handling
Figure 16.3 Hardware Standby Mode Timing
16.2.4
Module Stop Mode
Module stop mode can be set for individual on-chip peripheral modules.
When the corresponding bit in MSTPCR is set to 1, module operation stops at the end of the bus
cycle and a transition is made to module stop mode. The CPU continues operating independently.
When the corresponding bit is cleared to 0, module stop mode is cleared and the module starts
operating at the end of the bus cycle. In module stop mode, the internal states of modules other
than the SCI are retained.
After reset clearance, all modules other than the DMAC are in module stop mode.
The module registers which are set in module stop mode cannot be read or written to.
Rev. 2.00, 03/04, page 477 of 534