MCIMX357CJQ5C Freescale Semiconductor, MCIMX357CJQ5C Datasheet - Page 98

• Manufacturer Part Number: MCIMX357CJQ5C
• Description: MPU MX35 ARM11 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX357CJQ5C

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-MAPBGA
• Processor Series: i.MX357
• Core: ARM1136JF-S
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: I2C, JTAG, UART
• Maximum Clock Frequency: 532 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.33 V to 1.47 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

1
2
3
4.9.16
Figure 71
98
MLBCLK pulse width variation
MLBSIG/MLBDAT output high
impedance from MLBCLK low
OW1
OW2
OW3
OW4
MLBSIG/MLBDAT input valid
MLBSIG/MLBDAT input hold
The MLB Controller can shut off MLBCLK to place MediaLB in a low-power state.
Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge,
measured in ns peak-to-peak (pp)
The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
ID
MLBCLK high time
(BATT_LINE)
to MLBCLK falling
from MLBCLK low
1-Wire bus
Bus Hold Time
Parameter
depicts the RPP timing, and
Reset time low
Presence detect high
Presence detect low
Reset time high
1-Wire Timing Specifications
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
Table 61. RPP Sequence Delay Comparisons Timing Parameters
Figure 71. Reset and Presence Pulses (RPP) Timing Diagram
Table 60. MLB Device 1024Fs Timing Parameters (continued)
Parameters
Symbol
t
t
t
t
t
t
mpwv
dsmcf
dhmcf
mcfdz
“Reset Pulse”
mdzh
mckh
1-WIRE Tx
OW1
Table 61
Min
9.7
9.3
—
1
0
0
2
lists the RPP timing parameters.
t
t
t
t
RSTL
PDH
PDL
RSTH
10.6
10.2
Typ
—
—
—
—
—
Symbol
Max
t
0.7
mckl
—
—
—
—
—
OW3
OW2
480
15
60
480
“Presence Pulse”
Min.
DS2502 Tx
Units
ns pp
ns
ns
ns
ns
ns
Typ.
511
512
—
—
OW4
Freescale Semiconductor
Max.
240
PLL unlocked
60
—
—
Comment
Note
Note
—
—
—
2
3
Units
µs
µs
µs
µs