MCIMX357CJQ5C Freescale Semiconductor, MCIMX357CJQ5C Datasheet - Page 71

• Manufacturer Part Number: MCIMX357CJQ5C
• Description: MPU MX35 ARM11 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX357CJQ5C

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-MAPBGA
• Processor Series: i.MX357
• Core: ARM1136JF-S
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: I2C, JTAG, UART
• Maximum Clock Frequency: 532 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.33 V to 1.47 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

1
Display interface clock period average value.
Figure 51
parameters. The DISP3_IF_CLK_DOWN_WR and DISP3_IF_CLK_UP_WR parameters are set via the
DI_DISP3_TIME_CONF Register.
Freescale Semiconductor
Display interface clock period immediate value
IP10
IP11
IP12
IP13
IP14
IP15
IP9
DISPB_D3_VSYNC
DISPB_D3_HSYNC
DISPB_D3_DRDY
ID
DISPB_D3_CLK
depicts the synchronous display interface timing for access level, and
other controls
Table 52. Synchronous Display Interface Timing Parameters—Pixel Level (continued)
DISPB_DATA
Horizontal blank interval 1
Horizontal blank interval 2
HSYNC delay
Screen height
VSYNC width
Vertical blank interval 1
Vertical blank interval 2
Figure 51. Synchronous Display Interface Timing Diagram—Access Level
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
Parameter
IP16
Tdicp
IP17
=
T HSP_CLK
Symbol
IP19
Thbi1
Thbi2
Tvbi1
Tvbi2
Thsd
Tvsw
⋅
Tsh
DISP3_IF_CLK_PER_WR
----------------------------------------------------------------- -
HSP_CLK_PERIOD
IP18
IP20
BGXP × Tdpcp
(SCREEN_WIDTH – BGXP – FW) × Tdpcp
H_SYNC_DELAY × Tdpcp
(SCREEN_HEIGHT + 1) × Tsw
if V_SYNC_WIDTH_L = 0 than
(V_SYNC_WIDTH + 1) × Tdpcp
else
(V_SYNC_WIDTH + 1) × Tsw
BGYP × Tsw
(SCREEN_HEIGHT – BGYP – FH) × Tsw
Value
Table 53
lists the timing
Units
ns
ns
ns
ns
ns
ns
ns
71