MCIMX357CJQ5C Freescale Semiconductor, MCIMX357CJQ5C Datasheet - Page 109

• Manufacturer Part Number: MCIMX357CJQ5C
• Description: MPU MX35 ARM11 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX357CJQ5C

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-MAPBGA
• Processor Series: i.MX357
• Core: ARM1136JF-S
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: I2C, JTAG, UART
• Maximum Clock Frequency: 532 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.33 V to 1.47 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

4.9.18
Electrical and timing specifications of the parallel interface are presented in the subsequent sections.
4.9.19
This section describes the electrical information of the PWM. The PWM can be programmed to select one
of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before
being input to the counter. The output is available at the pulse-width modulator output (PWMO) external
Freescale Semiconductor
USB_Clk
USB_Data[7:0]
USB_Dir
USB_Stp
USB_Nxt
US15
US16
US17
ID
Name
USB_TXOE_B
USB_DAT_VP
USB_SE0_VM
USB_Dir/Nxt
USB_Data
USB_Clk
USB_Stp
Parallel Interface (ULPI) Timing
PWM Electrical Specifications
Direction
Out
I/O
In
In
In
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
Table 72. USB Timing Specification in VP_VM Unidirectional Mode
Figure 86. USB Transmit/Receive Waveform in Parallel Mode
Interface clock. All interface signals are synchronous to the clock.
Bidirectional data bus, driven low by the link during idle. Bus ownership is determined by Dir.
Direction. Control the direction of the data bus.
Stop. The link asserts this signal for 1 clock cycle to stop the data stream currently on the bus.
Next. The PHY asserts this signal to throttle the data.
US15
US15
Table 71. Signal Definitions—Parallel Interface
Parameter
US16
US16
US17
Signal Description
Min.
—
—
—
US17
Max.
6.0
0.0
9.0
Unit
ns
ns
ns
Reference Signal
Conditions /
10 pF
10 pF
10 pF
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