MCIMX357CJQ5C Freescale Semiconductor, MCIMX357CJQ5C Datasheet - Page 70

• Manufacturer Part Number: MCIMX357CJQ5C
• Description: MPU MX35 ARM11 400-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX357CJQ5C

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-MAPBGA
• Processor Series: i.MX357
• Core: ARM1136JF-S
• Data Bus Width: 32 bit
• Data Ram Size: 128 KB
• Interface Type: I2C, JTAG, UART
• Maximum Clock Frequency: 532 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.33 V to 1.47 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

of the DISPB_D3_CLK signal and active-low polarity of the DISPB_D3_HSYNC, DISPB_D3_VSYNC
and DISPB_D3_DRDY signals.
Figure 50
programmable.
Table 52
70
DISPB_D3_HSYNC
DISPB_D3_VSYNC
DISPB_D3_DRDY
DISPB_D3_HSYNC
DISPB_D3_DRDY
DISPB_D3_DATA
IP5
IP6
IP7
IP8
DISPB_D3_CLK
ID
Start of line
shows timing parameters of signals presented in
depicts the vertical timing (timing of one frame). All figure parameters shown are
Display interface clock period
Display pixel clock period
Screen width
HSYNC width
IP11
Table 52. Synchronous Display Interface Timing Parameters—Pixel Level
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
Figure 49. TFT Panels Timing Diagram—Horizontal Sync Pulse
Figure 50. TFT Panels Timing Diagram—Vertical Sync Pulse
Parameter
IP5
IP13
IP8
IP9
IP14
Symbol
Tdpcp
Tdicp
Thsw
Tsw
IP7
Figure 49
Tdicp
(DISP3_IF_CLK_CNT_D + 1) × Tdicp
(SCREEN_WIDTH + 1) × Tdpcp
(H_SYNC_WIDTH + 1) × Tdpcp
Start of frame
1
IP6
IP12
and
Figure
Value
50.
End of frame
Freescale Semiconductor
IP10
IP15
Units
ns
ns
ns
ns