EZ80F91NA050EC Zilog, EZ80F91NA050EC Datasheet - Page 245

• Manufacturer Part Number: EZ80F91NA050EC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050EC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No
• Other names: 269-3250

eZ80F91 MCU
Product Specification
236
ZDI Write Operations
ZDI Single-Byte Write
For single-byte Write operations, the address and write control bit are first written to the
ZDI block. Following the single-bit byte separator, the data is shifted into the ZDI block
on the next 8 rising edges of ZCL. The master terminates activity after 8 clock cycles.
Figure 53
displays the timing for ZDI single-byte Write operations.
ZDI Data Byte
ZCL
7
8
9
1
2
3
4
5
6
7
8
9
ZDA
A0
Write
0/1
D7
D6
D5
D4
D3
D2
D1
D0
1
msb
lsb
of DATA
of DATA
lsb of
Single-Bit
End of Data
ZDI Address
Byte Separator
or New ZDI
START Signal
Figure 53. ZDI Single-Byte Data Write Timing
ZDI Block Write
The block Write operation is initiated in the same manner as the single-byte Write opera-
tion, but instead of terminating the Write operation after the first data byte is transferred,
the ZDI master continues to transmit additional bytes of data to the ZDI slave on the
eZ80F91 device. After the receipt of each byte of data the ZDI register address increments
by 1. If the ZDI register address reaches the end of the Write Only ZDI register address
space (
), the address stops incrementing.
Figure 54
displays the timing for ZDI block
30h
Write operations.
PS019215-0910
Zilog Debug Interface