EZ80F91NA050EC Zilog, EZ80F91NA050EC Datasheet - Page 217

IC ACCLAIM MCU 256KB 144-BGA

EZ80F91NA050EC

Manufacturer Part Number
EZ80F91NA050EC
Description
IC ACCLAIM MCU 256KB 144-BGA
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Datasheets

Specifications of EZ80F91NA050EC

Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LBGA
Data Bus Width
8 bit
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
16 bit
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
No
Other names
269-3250

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80F91NA050EC
Manufacturer:
Zilog
Quantity:
10 000
Part Number:
EZ80F91NA050EC00TR
Manufacturer:
Zilog
Quantity:
10 000
Table 114. SPI Control Register
PS019215-0910
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit 
Position
7
IRQ_EN
6
5
SPI_EN
4
MASTER_EN
3
CPOL
2
CPHA
[1:0]
SPI Control Register
This register is used to control and setup the serial peripheral interface. The SPI must be
disabled prior to making any changes to CPHA or CPOL. See
Value Description
0
1
0
0
1
0
1
0
1
0
1
00
R/W
SPI system interrupt is disabled.
SPI system interrupt is enabled.
Reserved.
SPI is disabled.
SPI is enabled.
When enabled, the SPI operates as a slave.
When enabled, the SPI operates as a master.
Master SCK pin idles in a Low (0) state.
Master SCK pin idles in a High (1) state.
SS must go High after transfer of every byte of data.
SS remains Low to transfer any number of data bytes.
Reserved.
7
0
R
6
0
(SPI_CTL = 00BAh)
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
1
R
1
0
Table
Product Specification
Serial Peripheral Interface
114.
R
0
0
eZ80F91 MCU
208

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