EZ80F91NA050EC Zilog, EZ80F91NA050EC Datasheet - Page 152

• Manufacturer Part Number: EZ80F91NA050EC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050EC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No
• Other names: 269-3250

PS019215-0910
Timer Output Compare Control Register 2
The Timer3 Output Compare Control Register 2 (see
that occurs on the output compare pins when a timer compare happens.
Table 67. Timer Output Compare Control Register 2
3
OC1_INIT
2
OC0_INIT
1
MAST_MODE
0
OC_EN
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:6]
OC3_MODE
[5:4]
OC2_MODE
0
1
0
1
0
1
0
1
Value
00
01
10
11
00
01
10
11
R/W
7
0
OC pin cleared when initialized.
OC pin set when initialized.
OC pin cleared when initialized.
OC pin set when initialized.
OC pins are independent.
OC pins all mimic OC0.
OUTPUT COMPARE mode is disabled.
OUTPUT COMPARE mode is enabled.
Description
Initialize OC pin to value specified in
TMR3_OC_CTL1[OC3_INT].
OC pin is cleared upon timer compare.
OC pin is set upon timer compare.
OC pin toggles upon timer compare.
Initialize OC pin to value specified in
TMR3_OC_CTL1[OC2_INT].
OC pin is cleared upon timer compare.
OC pin is set upon timer compare.
OC pin toggles upon timer compare.
R/W
6
0
R/W
5
0
R/W
4
0
Table
R/W
67) is used to select the event
3
0
(TMR3_OC_CTL2 = 0081h)
Programmable Reload Timers
Product Specification
R/W
2
0
eZ80F91 MCU
R/W
1
0
R/W
0
0
143