EZ80F91NA050EC Zilog, EZ80F91NA050EC Datasheet - Page 224

• Manufacturer Part Number: EZ80F91NA050EC
• Description: IC ACCLAIM MCU 256KB 144-BGA
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F91NA050EC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: Ethernet, I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 16 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• For Use With: 269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: No
• Other names: 269-3250

PS019215-0910
Arbitration
Any master initiates a transfer if the bus is free. As a result, multiple masters each gener-
ates a START condition if the bus is free within a minimum period. If multiple masters
generate a START condition, a START is defined for the bus. However, arbitration defines
which MASTER controls the bus. Arbitration takes place on the SDA line. As mentioned,
START conditions are initiated only while the SCL line is held High. If during this period,
a master (M1) initiates a High-to-Low transition—that is, a START condition—while a
second master (M2) transmits a Low signal on the line, then the first master, M1, cannot
take control of the bus. As a result, the data output stage for M1 is disabled.
Arbitration continues for many bits. Its first stage is comparison of the address bits. If the
masters are each trying to address the same device, arbitration continues with a compari-
son of the data. Because address and data information on the I
tion, no information is lost during this process. A master that loses the arbitration
generates clock pulses until the end of the byte in which it loses the arbitration.
If a master also incorporates a slave function and it loses arbitration during the addressing
stage, it is possible that the winning master is trying to address it. The losing master must
switch over immediately to its slave receiver mode.
cedure for two masters. Of course, more masters can be involved, depending on how many
masters are connected to the bus. The moment there is a difference between the internal
data level of the master generating DATA 1 and the actual level on the SDA line, its data
output is switched off, which means that a High output level is then connected to the bus.
As a result, the data transfer initiated by the winning master is not affected. Because con-
trol of the I
there is no central master, nor any order of priority on the bus.
Special attention must be paid if, during a serial transfer, the arbitration procedure is still
in progress at the moment when a repeated START condition or a STOP condition is trans-
mitted to the I
CLK1 Signal
CLK2 Signal
SCL Signal
2
C bus is decided solely on the address and data sent by competing masters,
2
C bus. If it is possible for such a situation to occur, the masters involved
Figure 47. Clock Synchronization In I
State
Wait
Counter
Reset
Start Counting
High Period
Figure 47
2
C Protocol
2
displays the arbitration pro-
C bus is used for arbitra-
Product Specification
I
2
C Serial I/O Interface
215