ST10F272Z2Q3 STMicroelectronics, ST10F272Z2Q3 Datasheet - Page 24

• Manufacturer Part Number: ST10F272Z2Q3
• Description: MCU 16BIT 256KB FLASH 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F272Z2Q3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 64MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5579

Memory organization
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(only word accesses are possible). Two waitstates give an access time of 62.5 ns at 64 MHz
CPU clock. No tristate waitstate is used.
I2C: Address range 00’EA00h - 00’EAFFh is reserved for the I2C Module access. The I2C is
enabled by setting XPEN bit 2 of the SYSCON register and bit 9 of the XPERCON register.
Accesses to the I2C Module use demultiplexed addresses and a 16-bit data bus (only word
accesses are possible). Two waitstates give an access time of 62.5 ns at 64 MHz CPU
clock. No tristate waitstate is used.
X-Miscellaneous: Address range 00’EB00h - 00’EBFFh is reserved for the access to a set
of XBUS additional features. They are enabled by setting XPEN bit 2 of the SYSCON
register and bit 10 of the XPERCON register. Accesses to this additional features use
demultiplexed addresses and a 16-bit data bus (only word accesses are possible). Two
waitstates give an access time of 62.5 ns at 64 MHz CPU clock. No tristate waitstate is
used. The following set of features are provided:
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In order to meet the needs of designs where more memory is required than is provided on
chip, up to 16M Bytes of external memory can be connected to the microcontroller.
Visibility of XBUS peripherals
In order to keep the ST10F272Z2 compatible with the ST10F168 / ST10F269, the XBUS
peripherals can be selected to be visible on the external address / data bus. Different bits for
X-peripheral enabling in XPERCON register must be set. If these bits are cleared before the
global enabling with XPEN bit in SYSCON register, the corresponding address space, port
pins and interrupts are not occupied by the peripherals, thus the peripheral is not visible and
not available. Refer to
CLKOUT programmable divider
XBUS interrupt management registers
ADC multiplexing on P1L register
Port1L digital disable register for extra ADC channels
CAN2 multiplexing on P4.5/P4.6
CAN1-2 main clock prescaler
Main Voltage Regulator disable for power-down mode
TTL / CMOS threshold selection for Port0, Port1, and Port5.
Chapter 23: Register set on page
113.
ST10F272Z2