Z8F0413HH005EG Zilog, Z8F0413HH005EG Datasheet - Page 94

• Manufacturer Part Number: Z8F0413HH005EG
• Description: IC ENCORE MCU FLASH 4K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0413HH005EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SSOP
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-4108; Z8F0413HH005EG

PS024314-0308
ONE-SHOT Mode
CONTINUOUS Mode
COUNTER Mode
PWM SINGLE OUTPUT Mode
CAPTURE Mode
COMPARE Mode
GATED Mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
If the timer is enabled the Timer Output signal is complemented after timer reload.
0 = Count occurs on the rising edge of the Timer Input signal
1 = Count occurs on the falling edge of the Timer Input signal
0 = Timer Output is forced Low (0) when the timer is disabled. When enabled, the
Timer Output is forced High (1) upon PWM count match and forced Low (0) upon
Reload.
1 = Timer Output is forced High (1) when the timer is disabled. When enabled, the
Timer Output is forced Low (0) upon PWM count match and forced High (1) upon
Reload.
0 = Count is captured on the rising edge of the Timer Input signal
1 = Count is captured on the falling edge of the Timer Input signal
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
0 = Timer counts when the Timer Input signal is High (1) and interrupts are generated
on the falling edge of the Timer Input.
1 = Timer counts when the Timer Input signal is Low (0) and interrupts are generated
on the rising edge of the Timer Input.
Z8 Encore! XP
Product Specification
®
F0823 Series
Timers
84