Z8F0413HH005EG Zilog, Z8F0413HH005EG Datasheet - Page 87

• Manufacturer Part Number: Z8F0413HH005EG
• Description: IC ENCORE MCU FLASH 4K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0413HH005EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SSOP
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-4108; Z8F0413HH005EG

PS024314-0308
timer value is not reset to
the Timer Output pin changes state (from Low to High or from High to Low) upon
Compare.
If the Timer reaches
the steps below to configure a timer for COMPARE mode and to initiate the count:
1. Write to the Timer Control register to:
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the Compare value.
4. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing
5. If using the Timer Output function, configure the associated GPIO port pin for the
6. Write to the Timer Control register to enable the timer and initiate counting.
In COMPARE mode, the system clock always provides the timer input. The Compare time
can be calculated by the following equation:
GATED Mode
In GATED mode, the timer counts only when the Timer Input signal is in its active state
(asserted), as determined by the TPOL bit in the Timer Control register. When the Timer
Input signal is asserted, counting begins. A timer interrupt is generated when the Timer
Input signal is deasserted or a timer Reload occurs. To determine if a Timer Input signal
deassertion generated the interrupt, read the associated GPIO input value and compare to
the value stored in the TPOL bit.
The timer counts up to the 16-bit Reload value stored in the Timer Reload High and Low
Byte registers. The timer input is the system clock. When reaching the Reload value, the
timer generates an interrupt, the count value in the Timer High and Low Byte registers is
reset to
Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state
(from Low to High or from High to Low) at timer reset.
–
–
–
–
to the relevant interrupt registers.
Timer Output alternate function.
COMPARE Mode Time (s)
0001H
Disable the timer.
Configure the timer for Compare mode.
Set the prescale value.
Set the initial logic level (High or Low) for the Timer Output alternate function, if
appropriate.
and counting resumes (assuming the Timer Input signal remains asserted).
FFFFH
0001H
, the timer rolls over to
=
). Also, if the Timer Output alternate function is enabled,
(
---------------------------------------------------------------------------------------------------- -
Compare Value Start Value
System Clock Frequency (Hz)
0000H
–
Z8 Encore! XP
and continue counting. Follow
Product Specification
) Prescale
×
®
F0823 Series
Timers
77