Z8F0413HH005EG Zilog, Z8F0413HH005EG Datasheet - Page 32

• Manufacturer Part Number: Z8F0413HH005EG
• Description: IC ENCORE MCU FLASH 4K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0413HH005EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SSOP
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-4108; Z8F0413HH005EG

Reset Sources
PS024314-0308
Table 9. Reset and Stop Mode Recovery Characteristics and Latency
During a System Reset or Stop Mode Recovery, the IPO requires 4
Z8 Encore! XP F0823 Series device is held in Reset for 66 cycles of the Internal Precision
Oscillator. If the crystal oscillator is enabled in the Flash option bits, this reset period is
increased to 5000 IPO cycles. When a reset occurs because of a low voltage condition or
Power-On Reset, this delay is measured from the time that the supply voltage first exceeds
the POR level. If the external pin reset remains asserted at the end of the reset period, the
device remains in reset until the pin is deasserted.
At the beginning of Reset, all GPIO pins are configured as inputs with pull-up resistor
disabled.
During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal
oscillator and Watchdog Timer oscillator continue to run.
Upon Reset, control registers within the Register File that have a defined Reset value are
loaded with their reset values. Other control registers (including the Stack Pointer, Regis-
ter Pointer, and Flags) and general-purpose RAM are undefined following Reset. The eZ8
CPU fetches the Reset vector at Program Memory addresses
that value into the Program Counter. Program execution begins at the Reset vector
address.
When the control registers are re-initialized by a system reset, the system clock after reset
is always the IPO. The software must reconfigure the oscillator control block, such that the
correct system clock source is enabled and selected.
Table 10
Reset
Type
System
Reset
Stop Mode
Recovery
lists the possible sources of a System Reset.
Control Registers
Reset (as applicable)
Unaffected, except
WDT_CTL and OSC_CTL
registers
Reset Characteristics and Latency
Reset 66 Internal Precision Oscillator Cycles
Reset 66 Internal Precision Oscillator Cycles
CPU Reset Latency (Delay)
eZ8
+ IPO startup time
Z8 Encore! XP
0002H
Reset and Stop Mode Recovery
Product Specification
µ
s to start up. Then the
and
®
0003H
F0823 Series
and loads
22