PIC18F2220-I/SP Microchip Technology, PIC18F2220-I/SP Datasheet - Page 388

• Manufacturer Part Number: PIC18F2220-I/SP
• Description: IC MCU FLASH 2KX16 A/D 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2220-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 4KB (2K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI/I2C/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2220/2320/4220/4320
Timer2 .............................................................................. 127
Timer3 .............................................................................. 129
Timing Diagrams
DS39599G-page 386
Associated Registers ............................................... 128
MSSP Clock Shift ............................................. 127, 128
Operation ................................................................. 127
Postscaler. See Postscaler, Timer2.
PR2 Register .................................................... 127, 138
Prescaler. See Prescaler, Timer2.
TMR2 Register ......................................................... 127
TMR2 to PR2 Match Interrupt .................. 127, 128, 138
Associated Registers ............................................... 131
Operation ................................................................. 130
Oscillator .......................................................... 129, 131
Overflow Interrupt ............................................. 129, 131
Resetting, Using a Special Event Trigger
TMR3H Register ...................................................... 129
TMR3L Register ....................................................... 129
A/D Conversion ........................................................ 346
Acknowledge Sequence ........................................... 188
Asynchronous Reception ......................................... 205
Asynchronous Transmission .................................... 203
Asynchronous Transmission (Back to Back) ............ 203
Baud Rate Generator with Clock Arbitration ............ 182
BRG Reset Due to SDA Arbitration During
Brown-out Reset (BOR) ........................................... 331
Bus Collision During a Repeated Start
Bus Collision During a Repeated Start
Bus Collision During a Stop
Bus Collision During a Stop
Bus Collision During Start
Bus Collision During Start
Bus Collision for Transmit and Acknowledge ........... 189
Capture/Compare/PWM (CCP) ................................ 333
CLKO and I/O ........................................................... 330
Clock Synchronization .............................................. 175
Clock, Instruction Cycle .............................................. 57
Example SPI Master Mode (CKE = 0) ..................... 335
Example SPI Master Mode (CKE = 1) ..................... 336
Example SPI Slave Mode (CKE = 0) ....................... 337
Example SPI Slave Mode (CKE = 1) ....................... 338
External Clock (All Modes Except PLL) ................... 328
Fail-Safe Clock Monitor (FSCM) .............................. 250
First Start Bit ............................................................ 183
Full-Bridge PWM Output .......................................... 146
Half-Bridge PWM Output .......................................... 145
I
I
I
I
I
I
I
2
2
2
2
2
2
2
C Bus Data ............................................................ 340
C Bus Start/Stop Bits ............................................. 339
C Master Mode (Transmission,
C Slave Mode (Transmission, 10-Bit Address) ...... 173
C Slave Mode (Transmission, 7-Bit Address) ........ 171
C Slave Mode with SEN = 0 (Reception,
C Slave Mode with SEN = 0 (Reception,
Output (CCP) ................................................... 131
Start Condition ................................................. 191
Condition (Case 1) ........................................... 192
Condition (Case 2) ........................................... 192
Condition (Case 1) ........................................... 193
Condition (Case 2) ........................................... 193
Condition (SCL = 0) ......................................... 191
Condition (SDA Only) ....................................... 190
7 or 10-Bit Address) ......................................... 186
10-Bit Address) ................................................ 172
7-Bit Address) .................................................. 170
I
I
Low-Voltage Detect ................................................. 234
Low-Voltage Detect Characteristics ......................... 322
Master SSP I
Master SSP I
Parallel Slave Port (PIC18F4X20) ........................... 334
Parallel Slave Port (PSP) Read ............................... 115
Parallel Slave Port (PSP) Write ............................... 115
PWM Auto-Shutdown (PRSEN = 0,
PWM Auto-Shutdown (PRSEN = 1,
PWM Direction Change ........................................... 148
PWM Direction Change at Near
PWM Output ............................................................ 138
Repeat Start Condition ............................................ 184
Reset, Watchdog Timer (WDT), Oscillator Start-up
Slave Mode General Call Address Sequence
Slave Synchronization ............................................. 161
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 160
SPI Mode (Slave Mode with CKE = 0) ..................... 162
SPI Mode (Slave Mode with CKE = 1) ..................... 162
Stop Condition Receive or Transmit Mode .............. 188
Synchronous Transmission ..................................... 206
Synchronous Transmission (Through TXEN) .......... 207
Time-out Sequence on POR w/
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 332
Transition for Entry to SEC_IDLE Mode .................... 34
Transition for Entry to SEC_RUN Mode .................... 36
Transition for Entry to Sleep Mode ............................ 32
Transition for Two-Speed Start-up
Transition for Wake from PRI_IDLE Mode ................ 33
Transition for Wake from RC_RUN Mode
Transition for Wake from
Transition for Wake from Sleep (HSPLL) .................. 32
Transition to PRI_IDLE Mode .................................... 33
Transition to RC_IDLE Mode ..................................... 35
Transition to RC_RUN Mode ..................................... 37
USART Synchronous Receive (Master/Slave) ........ 344
USART Synchronous Reception
USART SynchronousTransmission (Master/Slave) . 344
2
2
C Slave Mode with SEN = 1 (Reception,
C Slave Mode with SEN = 1 (Reception,
10-Bit Address) ................................................ 177
7-Bit Address) .................................................. 176
Auto-Restart Disabled) .................................... 151
Auto-Restart Enabled) ..................................... 151
100% Duty Cycle ............................................. 148
Timer (OST), Power-up Timer (PWRT) ........... 331
(7 or 10-Bit Addressing Mode) ......................... 178
V
PLL Enabled (MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
(INTOSC to HSPLL) ........................................ 248
(RC_RUN to PRI_RUN) ..................................... 35
SEC_RUN Mode (HSPLL) ................................. 34
(Master Mode, SREN) ..................................... 208
DD
Rise > T
2
2
C Bus Data ........................................ 342
C Bus Start/Stop Bits ........................ 342
PWRT
© 2007 Microchip Technology Inc.
DD
) ............................................ 51
, V
DD
DD
DD
): Case 1 ....................... 50
): Case 2 ....................... 50
Rise T
DD
DD
,
PWRT
) ..................... 51
) .............. 50