PIC18F2220-I/SP Microchip Technology, PIC18F2220-I/SP Datasheet
PIC18F2220-I/SP
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... PIC18F2220/2320/4220/4320 Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology © 2007 Microchip Technology Inc. 28/40/44-Pin High-Performance, Data Sheet DS39599G ...
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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F4220 4096 2048 PIC18F4320 8192 4096 © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Peripheral Highlights: • High-Current Sink/Source 25 mA/25 mA • Three External Interrupts • Capture/Compare/PWM (CCP) modules: - Capture is 16-bit, max. resolution is 6. Compare is 16-bit, max. resolution is 100 PWM output: PWM resolution 10-bit • ...
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... PIC18F2220/2320/4220/4320 Pin Diagrams 28-Pin SPDIP, SOIC RA2/AN2/V RA3/AN3/V RA4/T0CKI/C1OUT RA5/AN4/SS/LVDIN/C2OUT OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1/P1A RC3/SCK/SCL 40-Pin PDIP MCLR/V RA2/AN2/V REF RA3/AN3/V RA4/T0CKI/C1OUT RA5/AN4/SS/LVDIN/C2OUT RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2* RC2/CCP1/P1A RC3/SCK/SCL RD0/PSP0 RD1/PSP1 * RB3 is the alternate pin for the CCP2 pin multiplexing. ...
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... RB2/AN8/INT2 RB3/AN9/CCP2* * RB3 is the alternate pin for the CCP2 pin multiplexing. 44-Pin QFN RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RB0/AN12/INT0 RB1/AN10/INT1 RB2/AN8/INT2 * RB3 is the alternate pin for the CCP2 pin multiplexing. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 RC0/T1OSO/T1CKI OSC2/CLKO/RA6 3 OSC1/CLKI/RA7 30 4 PIC18F4220 ...
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... Appendix E: Migration from Mid-range to Enhanced Devices............................................................................................................ 378 Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 378 Index .................................................................................................................................................................................................. 379 The Microchip Web Site ..................................................................................................................................................................... 389 Customer Change Notification Service .............................................................................................................................................. 389 Customer Support .............................................................................................................................................................................. 389 Reader Response .............................................................................................................................................................................. 390 PIC18F2220/2320/4220/4320 Product Identification System ............................................................................................................ 391 DS39599G-page 4 © 2007 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 DS39599G-page 5 ...
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... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 6 © 2007 Microchip Technology Inc. ...
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... Timer have been reduced 80%, with typical values of 1.8 and 2.2 μA, respectively. 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F2220/2320/4220/4320 family offer nine different oscillator options, allowing users a wide range of choices in developing application hardware. These include: • Four Crystal modes using crystals or ceramic resonators. • ...
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... PIC18F2220/2320/4220/4320 1.3 Details on Individual Family Members Devices in the PIC18F2220/2320/4220/4320 family are available in 28-pin (PIC18F2X20) and 40/44-pin (PIC18F4X20) packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in five ways: 1. Flash ...
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... FIGURE 1-1: PIC18F2220/2320 BLOCK DIAGRAM Table Pointer <2> 21 inc/dec logic 21 21 PCLATU 20 Address Latch Program Memory PCU (4 Kbytes) Program Counter Data Latch 16 Table Latch 8 ROM Latch Instruction Register Instruction Decode & Control (2) OSC1 Power-up Internal Timer Oscillator (2) Block OSC2 Oscillator Start-up Timer ...
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... PIC18F2220/2320/4220/4320 FIGURE 1-2: PIC18F4220/4320 BLOCK DIAGRAM Table Pointer <2> 21 inc/dec logic 21 21 PCLATU 20 Address Latch Program Memory PCU (8 Kbytes) Program Counter Data Latch 16 Table Latch 8 ROM Latch Instruction Register Instruction Decode & Control Internal (3) OSC1 Power-up Oscillator Block (3) OSC2 Oscillator Start-up Timer ...
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... TABLE 1-2: PIC18F2220/2320 PINOUT I/O DESCRIPTIONS Pin Number Pin Pin Name PDIP SOIC MCLR MCLR V PP OSC1/CLKI/RA7 9 9 OSC1 CLKI RA7 OSC2/CLKO/RA6 10 10 OSC2 CLKO RA6 RA0/AN0 2 2 RA0 AN0 RA1/AN1 3 3 RA1 AN1 RA2/AN2/V -/ REF REF RA2 AN2 V - REF CV REF ...
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... PIC18F2220/2320/4220/4320 TABLE 1-2: PIC18F2220/2320 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Pin Name PDIP SOIC RB0/AN12/INT0 21 21 RB0 AN12 INT0 RB1/AN10/INT1 22 22 RB1 AN10 INT1 RB2/AN8/INT2 23 23 RB2 AN8 INT2 RB3/AN9/CCP2 24 24 RB3 AN9 (1) CCP2 RB4/AN11/KBI0 25 25 RB4 AN11 KBI0 RB5/KBI1/PGM ...
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... TABLE 1-2: PIC18F2220/2320 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Pin Name PDIP SOIC RC0/T1OSO/T1CKI 11 11 RC0 T1OSO T1CKI RC1/T1OSI/CCP2 12 12 RC1 T1OSI (2) CCP2 RC2/CCP1/P1A 13 13 RC2 CCP1 P1A RC3/SCK/SCL 14 14 RC3 SCK SCL RC4/SDI/SDA 15 15 RC4 SDI SDA RC5/SDO 16 16 ...
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... PIC18F2220/2320/4220/4320 TABLE 1-3: PIC18F4220/4320 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PDIP TQFP QFN MCLR/V /RE3 MCLR V PP RE3 OSC1/CLKI/RA7 13 30 OSC1 CLKI RA7 OSC2/CLKO/RA6 14 31 OSC2 CLKO RA6 RA0/AN0 2 19 RA0 AN0 RA1/AN1 3 20 RA1 AN1 RA2/AN2/V -/ REF REF RA2 ...
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... OD = Open-drain (no diode to V Note 1: Alternate assignment for CCP2 when CCP2MX is cleared. 2: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Pin Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. ...
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... PIC18F2220/2320/4220/4320 TABLE 1-3: PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP TQFP QFN RC0/T1OSO/T1CKI 15 32 RC0 T1OSO T1CKI RC1/T1OSI/CCP2 16 35 RC1 T1OSI (2) CCP2 RC2/CCP1/P1A 17 36 RC2 CCP1 P1A RC3/SCK/SCL 18 37 RC3 SCK SCL RC4/SDI/SDA 23 42 RC4 SDI SDA RC5/SDO ...
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... OD = Open-drain (no diode to V Note 1: Alternate assignment for CCP2 when CCP2MX is cleared. 2: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Pin Buffer Type Type PORTD is a bidirectional I/O port or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when PSP module is enabled ...
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... PIC18F2220/2320/4220/4320 TABLE 1-3: PIC18F4220/4320 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PDIP TQFP QFN RE0/AN5/ RE0 AN5 RD RE1/AN6/ RE1 AN6 WR RE2/AN7/ RE2 AN7 CS RE3 — — Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open-drain (no diode to V Note 1: Alternate assignment for CCP2 when CCP2MX is cleared ...
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... The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a fre- quency out of the crystal manufacturers specifications. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 FIGURE 2-1: (1) C1 (1) C2 Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2 ...
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... PIC18F2220/2320/4220/4320 TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Typical Capacitor Values Crystal Tested: Osc Type Freq kHz 33 pF 200 kHz MHz MHz MHz MHz MHz 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation ...
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... Clock from Ext. System PIC18FXXXX RA6 I/O (OSC2) © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 2.5 RC Oscillator For timing insensitive applications, the “RC” and “RCIO” device options offer additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (R ues and the operating temperature ...
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... PIC18F2220/2320/4220/4320 2.6 Internal Oscillator Block The PIC18F2X20/4X20 devices include an internal oscillator block that generates two independent clock signals. Either can be used as the system’s clock source. This can eliminate the need for external oscillator circuits on the OSC1 or OSC2 pins. The main output (INTOSC 8-MHz clock source that can be used to directly drive the system clock ...
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... TUN<0>: A placeholder with no effect on the INTRC frequency. Provided to facilitate incrementation and decrementation of the OSCTUN2 register and adjustment of the INTRC frequency. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 When the OSCTUNE register is modified, the INTOSC and INTRC frequencies begin shifting to the new fre- quency. The INTOSC and INTRC clocks will stabilize at the new frequency within 100 μ ...
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... PIC18F2220/2320/4220/4320 2.6.3 OSCTUN2 REGISTER The internal oscillator block is calibrated at the factory to produce an INTRC output frequency of approxi- mately 31 kHz. (See parameters F20 and F21 in Table 26-8.) The INTRC frequency can be adjusted two ways: • If TUNSEL (OSCTUN2<7>) is clear – TUN5:TUN1 in OSCTUNE<5:1> adjusts the INTRC clock frequency and also can adjust the INTOSC clock frequency ...
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... Module” for further details of the Timer1 oscillator. See Section 23.1 “Configuration Bits” for Configuration register details. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 2.7.1 OSCILLATOR CONTROL REGISTER The OSCCON register (Register 2-3) controls sev- eral aspects of the system clock’s operation, both in full-power operation and in power-managed modes ...
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... PIC18F2220/2320/4220/4320 FIGURE 2-8: PIC18F2X20/4X20 CLOCK DIAGRAM Primary Oscillator OSC2 Sleep OSC1 Secondary Oscillator T1OSO T1OSCEN Enable Oscillator T1OSI OSCCON<6:4> Internal Oscillator Block INTRC Source DS39599G-page 26 PIC18F2X20/4X20 CONFIG1H <3:0> HSPLL 4 x PLL LP, XT, HS, RC, EC Clock Source Option for Other Modules OSCCON<6:4> 8 MHz ...
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... Internal oscillator block (RC modes Timer1 oscillator (Secondary modes Primary oscillator (Sleep and PRI_IDLE modes) Note 1: Depends on state of IESO bit in Configuration Register 1H. 2: SCS0 may not be set while T1OSCEN (T1CON<3>) is clear. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 (1) R/W-0 R R-0 IRCF0 OSTS IOFS U = Unimplemented bit, read as ‘ ...
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... PIC18F2220/2320/4220/4320 2.7.2 OSCILLATOR TRANSITIONS The PIC18F2X20/4X20 devices contain circuitry to pre- vent clocking “glitches” when switching between clock sources. A short pause in the system clock occurs dur- ing the clock switch. The length of this pause is between 8 and 9 clock periods of the new clock source. ...
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... Note 1: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 For PIC18F2X20/4X20 devices, the power-managed modes are invoked by using the existing SLEEP instruction. All modes exit to PRI_RUN mode when trig- gered by an interrupt, a Reset WDT time-out (PRI_RUN mode is the normal full-power execution mode ...
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... PIC18F2220/2320/4220/4320 3.1.2 ENTERING POWER-MANAGED MODES In general, entry, exit and switching between power- managed clock sources requires clock source switching. In each case, the sequence of events is the same. Any change in the power-managed mode begins with loading the OSCCON register and executing a SLEEP instruction. The SCS1:SCS0 bits select one of three power-managed clock sources ...
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... Clearing IDLEN allows the CPU to be clocked. Setting IDLEN disables clocks to the CPU, effectively stopping program execution (see Register 2-3). The peripherals continue to be clocked regardless of the setting of the IDLEN bit. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 WDT Peripherals are Time-out Clocked by ... Causes a ... ...
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... PIC18F2220/2320/4220/4320 FIGURE 3-1: TIMING TRANSITION FOR ENTRY TO SLEEP MODE OSC1 CPU Clock Peripheral Clock Sleep Program PC Counter FIGURE 3-2: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) OSC1 (1) T OST PLL Clock Output CPU Clock Peripheral Clock Program PC Counter Wake-up Event Note 1024 T ...
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... Program PC Counter Wake-up Event © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 When a wake-up event occurs, the CPU is clocked from the primary clock source. A delay of approxi- mately 10 μs is required between the wake-up event and when code execution starts. This is required to allow the CPU to become ready to execute instructions. ...
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... PIC18F2220/2320/4220/4320 3.3.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered by setting the IDLEN bit, modifying to SCS1:SCS0 = 01 and executing a SLEEP instruction. When the clock source is switched to the Timer1 oscillator (see Figure 3-5), the primary oscillator is shut down, the OSTS bit is cleared and the T1RUN bit is set ...
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... OST OSC PLL © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 was executed and the INTOSC source was already stable, the IOFS bit will remain set. If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source ...
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... PIC18F2220/2320/4220/4320 3.4 Run Modes If the IDLEN bit is clear when a SLEEP instruction is executed, the CPU and peripherals are both clocked from the source selected using the SCS1:SCS0 bits. While these operating modes may not afford the power conservation of Idle or Sleep modes, they do allow the device to continue executing instructions by using a lower frequency clock source ...
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... CPU Clock Peripheral Clock Program PC Counter © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Note: Caution should be used when modifying a single IRCF bit possible to select a higher clock speed than is supported by the low V Improper device operation may result if the V If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear ...
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... PIC18F2220/2320/4220/4320 3.4.4 EXIT TO IDLE MODE An exit from a power-managed Run mode to its corre- sponding Idle mode is executed by setting the IDLEN bit and executing a SLEEP instruction. The CPU is halted at the beginning of the instruction following the SLEEP instruction. There are no changes to any of the clock source status bits (OSTS, IOFS or T1RUN). ...
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... Execution continues during the INTOSC stabilization period. 5: Required delay when waking from Sleep and all Idle modes. This delay runs concurrently with any other required delays (see Section 3.3 “Idle Modes”). © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Clock Ready Power-Managed Status Bit Mode Exit Delay ...
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... PIC18F2220/2320/4220/4320 3.5.2 EXIT BY RESET Normally, the device is held in Reset by the Oscillator Start-up Timer (OST) until the primary clock (defined in Configuration Register 1H) becomes ready. At that time, the OSTS bit is set and the device begins executing code. Code execution can begin before the primary clock becomes ready. If either the Two-Speed Start-up (see Section 23.3 “ ...
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... If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast – decrement OSCTUNE. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 3.6.3 EXAMPLE – CCP IN CAPTURE MODE A CCP module can use free-running Timer1 (or Timer3), clocked by the internal oscillator block and an external event with a known period (i ...
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... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 42 © 2007 Microchip Technology Inc. ...
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... Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-1 for time-out situations. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Most registers are not affected by a WDT wake-up since this is viewed as the resumption of normal oper- ation ...
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... PIC18F2220/2320/4220/4320 4.1 Power-on Reset (POR) A Power-on Reset pulse is generated on-chip when V rise is detected. To take advantage of the POR cir- DD cuitry, just tie the MCLR pin through a resistor ( kΩ This will eliminate external RC compo- DD nents usually needed to create a Power-on Reset delay. A minimum rise rate for V DD (parameter D004) ...
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... Legend unchanged unknown unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h). © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 (2) Power-up and Brown-out PWRTEN = 1 ...
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... PIC18F2220/2320/4220/4320 TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices TOSU 2220 2320 4220 4320 TOSH 2220 2320 4220 4320 TOSL 2220 2320 4220 4320 STKPTR 2220 2320 4220 4320 PCLATU 2220 2320 4220 4320 PCLATH 2220 2320 4220 4320 ...
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... See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 MCLR Resets Power-on Reset, WDT Reset Brown-out Reset ...
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... PIC18F2220/2320/4220/4320 TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices ADRESH 2220 2320 4220 4320 ADRESL 2220 2320 4220 4320 ADCON0 2220 2320 4220 4320 ADCON1 2220 2320 4220 4320 ADCON2 2220 2320 4220 4320 CCPR1H 2220 2320 4220 4320 ...
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... See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 MCLR Resets Power-on Reset, WDT Reset Brown-out Reset ...
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... PIC18F2220/2320/4220/4320 FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
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... TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED MCLR Internal POR PWRT Time-out OST Time-out PLL Time-out Internal Reset Note 1024 clock cycles. OST ≈ max. First three stages of the PWRT timer. T PLL © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 , V RISE > PWRT T OST T PWRT T OST T ...
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... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 52 © 2007 Microchip Technology Inc. ...
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... Kbytes of Flash memory and can store up to 4,096 single-word instructions. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. The Program Memory Maps for PIC18F2220/4220 and PIC18F2320/4320 devices are shown in Figure 5-1 and Figure 5-2, respectively. FIGURE 5-2: PC< ...
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... PIC18F2220/2320/4220/4320 5.2 Return Address Stack The return address stack allows any combination program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL instruction is executed or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions ...
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... POP instruction. The POP instruc- tion discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 R/W-0 R/W-0 R/W-0 SP4 SP3 SP2 U = Unimplemented bit, read as ‘ ...
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... PIC18F2220/2320/4220/4320 5.3 Fast Register Stack A “fast return” option is available for interrupts. A Fast Register Stack is provided for the STATUS, WREG and BSR registers and are only one in depth. The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt ...
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... All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 5.6 Instruction Flow/Pipelining An “ ...
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... PIC18F2220/2320/4220/4320 5.7 Instructions in Program Memory The program memory is addressed in bytes. Instruc- tions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). Figure 5-5 shows an example of how instruction words are stored in the pro- gram memory ...
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... The Table Read/Table Write operation is discussed further in Section 6.1 “Table Reads and Table Writes”. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 5.9 Data Memory Organization The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory ...
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... PIC18F2220/2320/4220/4320 FIGURE 5-6: DATA MEMORY MAP FOR PIC18F2X20/4X20 DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh = 0010 Bank 1110 Bank 14 00h = 1111 Bank 15 FFh DS39599G-page 60 Data Memory Map 000h Access RAM 07Fh 080h GPR 0FFh 100h GPR 1FFh 200h Unused Read ‘ ...
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... This register is not available on PIC18F2X20 devices. 2: This is not a physical register. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 “core” are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. The SFRs are typically distributed among the peripherals whose functions they control ...
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... PIC18F2220/2320/4220/4320 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320) File Name Bit 7 Bit 6 Bit 5 TOSU — — — TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) STKPTR STKFUL STKUNF — PCLATU — — bit 21 PCLATH Holding Register for PC<15:8> PCL PC Low Byte (PC<7:0>) TBLPTRU — ...
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... TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 OSCCON IDLEN IRCF2 IRCF1 LVDCON — — IRVST WDTCON — — — RCON IPEN — — TMR1H Timer1 Register High Byte TMR1L Timer1 Register Low Byte T1CON RD16 T1RUN ...
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... PIC18F2220/2320/4220/4320 TABLE 5-2: REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 EEADR EEPROM Address Register EEDATA EEPROM Data Register EECON2 EEPROM Control Register 2 (not a physical register) EECON1 EEPGD CFGS — IPR2 OSCFIP CMIP — PIR2 OSCFIF CMIF — PIE2 ...
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... The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 3: The MOVFF instruction embeds the entire 12-bit address in the instruction. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 5.11 Bank Select Register (BSR) The need for a large general purpose memory space dictates a RAM banking scheme ...
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... PIC18F2220/2320/4220/4320 5.12 Indirect Addressing, INDF and FSR Registers Indirect Addressing is a mode of addressing data mem- ory, where the data memory address in the instruction is not fixed. An FSR register is used as a pointer to the data memory location that read or written. Since this pointer is in RAM, the contents can be modified by the program ...
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... Instruction Executed Opcode BSR<3:0> Instruction Fetched Opcode FIGURE 5-9: INDIRECT ADDRESSING 3 11 Note 1: For register file map detail, see Table 5-1. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 0h RAM Address FFFh 12 File Address = access of an Indirect Addressing register File FSR Indirect Addressing ...
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... PIC18F2220/2320/4220/4320 5.13 STATUS Register The STATUS register, shown in Register 5-2, contains the arithmetic status of the ALU. The STATUS register can be the operand for any instruction as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC bits, then the write to these five bits is disabled ...
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... A Brown-out Reset has not occurred (set by firmware only Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Note 1: If the BOREN Configuration bit is set (Brown-out Reset enabled), the BOR bit is ‘1’ Power-on Reset. After a Brown- ...
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... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 70 © 2007 Microchip Technology Inc. ...
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... Note 1: Table Pointer points to a byte in program memory. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 The program memory space is 16 bits wide while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces DD through an 8-bit register (TABLAT) ...
Page 74
... PIC18F2220/2320/4220/4320 FIGURE 6-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. ...
Page 75
... Initiates a memory read (Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 Read completed Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 R/W-0 R/W-x R/W-0 (1) FREE WRERR WREN U = Unimplemented bit, read as ‘ ...
Page 76
... PIC18F2220/2320/4220/4320 6.2.2 TABLAT – TABLE LATCH REGISTER The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TBLPTR – TABLE POINTER REGISTER The Table Pointer (TBLPTR) register addresses a byte within the program memory ...
Page 77
... MOVFW TABLAT MOVWF WORD_ODD © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT ...
Page 78
... PIC18F2220/2320/4220/4320 6.4 Erasing Flash Program Memory The minimum erase block size is 32 words or 64 bytes under firmware control. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in Flash memory is not supported. ...
Page 79
... CFGS bit to access program memory; • set WREN bit to enable byte writes. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction has to be executed 8 times for each programming operation. All of the table write operations will essentially be short writes because only the holding registers are written ...
Page 80
... PIC18F2220/2320/4220/4320 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW D'64 MOVWF COUNTER MOVLW BUFFER_ADDR_HIGH MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL READ_BLOCK TBLRD*+ MOVFW TABLAT MOVWF POSTINC0 DECFSZ COUNTER GOTO READ_BLOCK ...
Page 81
... OSCFIE CMIE — Legend unknown unchanged reserved unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 ; disable interrupts ; required sequence ; write 55H ; write AAH ; start program (CPU stall) ; re-enable interrupts ; loop until done ...
Page 82
... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 80 © 2007 Microchip Technology Inc. ...
Page 83
... EEPROM memory. When clear, oper- ations will access the data EEPROM memory. When set, program memory is accessed. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Control bit, CFGS, determines if the access will be to the Configuration registers or to program memory/data EEPROM memory. When set, subsequent operations access Configuration registers ...
Page 84
... PIC18F2220/2320/4220/4320 REGISTER 7-1: EECON1: DATA EEPROM CONTROL REGISTER 1 R/W-x R/W-x U-0 EEPGD CFGS — bit 7 Legend Settable bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory ...
Page 85
... SLEEP BCF EECON1, WREN © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruc- tion ...
Page 86
... PIC18F2220/2320/4220/4320 7.7 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in Configuration Words. External read and write opera- tions are disabled if either of these mechanisms are enabled. The microcontroller itself can both read and write to the internal Data EEPROM regardless of the state of the code-protect Configuration bit. Refer to Section 23.0 “ ...
Page 87
... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 8.2 Operation Example 8-1 shows the sequence unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. ...
Page 88
... PIC18F2220/2320/4220/4320 Example 8-3 shows the sequence unsigned multiply. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES3:RES0. EQUATION 8- UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L • ARG2H:ARG2L RES3:RES0 = (ARG1H • ARG2H • (ARG1H • ARG2L • 2 (ARG1L • ARG2H • 2 (ARG1L • ...
Page 89
... Individual inter- rupts can be disabled through their corresponding enable bits. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PIC bility mode, the interrupt priority bits for each source have no effect. INTCON< ...
Page 90
... PIC18F2220/2320/4220/4320 FIGURE 9-1: INTERRUPT LOGIC PSPIF PSPIE PSPIP ADIF ADIE ADIP RCIF RCIE RCIP Additional Peripheral Interrupts High-Priority Interrupt Generation Low-Priority Interrupt Generation PSPIF PSPIE PSPIP ADIF ADIE ADIP RCIF RCIE RCIP Additional Peripheral Interrupts DS39599G-page 88 TMR0IF TMR0IE TMR0IP RBIF RBIE ...
Page 91
... Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit ...
Page 92
... PIC18F2220/2320/4220/4320 REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values ...
Page 93
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 R/W-0 R/W-0 U-0 ...
Page 94
... PIC18F2220/2320/4220/4320 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Flag registers (PIR1, PIR2). REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0 R/W-0 ...
Page 95
... No TMR1 or TMR3 register capture occurred Compare mode TMR1 or TMR3 register compare match occurred (must be cleared in software TMR1 or TMR3 register compare match occurred PWM mode: Unused in this mode. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 R/W-0 R/W-0 R/W-0 EEIF BCLIF LVDIF U = Unimplemented bit, read as ‘0’ ...
Page 96
... PIC18F2220/2320/4220/4320 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of periph- eral interrupt sources, there are two Peripheral Inter- rupt Enable registers (PIE1, PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts ...
Page 97
... Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 R/W-0 R/W-0 R/W-0 EEIE BCLIE LVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 ...
Page 98
... PIC18F2220/2320/4220/4320 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of periph- eral interrupt sources, there are two Peripheral Inter- rupt Priority registers (IPR1, IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
Page 99
... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 R/W-1 R/W-1 R/W-1 EEIP BCLIP LVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 100
... PIC18F2220/2320/4220/4320 9.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from power- managed mode. RCON also contains the bit that enables interrupt priorities (IPEN). REGISTER 9-10: RCON: RESET CONTROL REGISTER R/W-0 U-0 U-0 IPEN — ...
Page 101
... MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 9.8 PORTB Interrupt-on-Change An input change on PORTB<7:4> sets flag bit, RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON<3>). Interrupt priority for PORTB interrupt-on-change is determined by the value contained in the interrupt priority bit, RBIP (INTCON2< ...
Page 102
... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 100 © 2007 Microchip Technology Inc. ...
Page 103
... PORT Note 1: I/O pins have diode protection to V © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 10.1 PORTA, TRISA and LATA Registers PORTA is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i ...
Page 104
... PIC18F2220/2320/4220/4320 FIGURE 10-2: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS RD LATA Data Bus LATA or PORTA CK Q Data Latch TRISA CK Q Analog Input TRIS Latch Mode RD TRISA PORTA SS Input (RA5 only) To A/D Converter and LVD Modules Note 1: I/O pins have protection diodes to V FIGURE 10-3: ...
Page 105
... Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Buffer Function TTL Input/output or analog input. ...
Page 106
... PIC18F2220/2320/4220/4320 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
Page 107
... CK Data Latch D WR TRISB CK TRIS Latch RD TRISC RD PORTB CCP2 Input Analog Input Mode To A/D Converter Note 1: I/O pins have diode protection to V © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 FIGURE 10- (2) RBPU Weak P Pull-up Data Bus WR LATB (1) or PORTB I/O pin WR TRISB ...
Page 108
... PIC18F2220/2320/4220/4320 TABLE 10-3: PORTB FUNCTIONS Name Bit# Buffer (1) RB0/AN12/INT0 bit 0 TTL (1) RB1/AN10/INT1 bit 1 TTL (1) RB2/AN8/INT2 bit 2 TTL (1) RB3/AN9/CCP2 bit 3 TTL RB4/AN11/KBI0 bit 4 TTL RB5/KBI1/PGM bit 5 TTL/ST RB6/KBI2/PGC bit 6 TTL/ST RB7/KBI3/PGD bit 7 TTL/ST Legend: TTL = TTL input Schmitt Trigger input Note 1: This buffer is a TTL input when configured as digital I/O. ...
Page 109
... Port/Peripheral Select signal selects between port data (output) and peripheral output. 3: Peripheral Output Enable is only active if Peripheral Select is active. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Note Power-on Reset, these pins are configured as digital inputs. The contents of the TRISC register are affected by peripheral overrides ...
Page 110
... PIC18F2220/2320/4220/4320 TABLE 10-5: PORTC FUNCTIONS Name Bit# Buffer Type RC0/T1OSO/T1CKI bit 0 ST RC1/T1OSI/CCP2 bit 1 ST (1) RC2/CCP1/P1A bit 2 ST RC3/SCK/SCL bit 3 ST RC4/SDI/SDA bit 4 ST RC5/SDO bit 5 ST RC6/TX/CK bit 6 ST RC7/RX/DT bit 7 ST Legend Schmitt Trigger input Note 1: Enhanced PWM output is available only on PIC18F4X20 devices. ...
Page 111
... PSP Write Note 1: I/O pins have diode protection to V © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 PORTD can also be configured as an 8-bit wide micro- processor port (Parallel Slave Port) by setting control bit, PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. See Section 10.6 “Parallel Slave Port” ...
Page 112
... PIC18F2220/2320/4220/4320 FIGURE 10-12: BLOCK DIAGRAM OF RD4:RD0 PINS PORTD/CCP1 Select PSPMODE RD LATD Data Bus D WR LATD or PORTD CK Data Latch D WR TRISD CK TRIS Latch PSP Read RD TRISD RD PORTD PSP Write Note 1: I/O pins have diode protection to V TABLE 10-7: PORTD FUNCTIONS Name Bit# ...
Page 113
... Master Clear input. In either configuration, RE3 also functions as the programming voltage input during programming. Note Power-on Reset, RE3 is enabled as a digital input only if Master Clear functionality is disabled. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 EXAMPLE 10-5: CLRF PORTE CLRF LATE MOVLW 0x0A MOVWF ADCON1 ...
Page 114
... PIC18F2220/2320/4220/4320 FIGURE 10-14: BLOCK DIAGRAM OF MCLR/V /RE3 PIN PP MCLRE Data Bus RD TRISE Schmitt Trigger RD LATE Latch PORTE High-Voltage Detect HV Internal MCLR Filter Low-Level MCLR Detect REGISTER 10-1: TRISE REGISTER R-0 R-0 R/W-0 IBF OBF IBOV bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘ ...
Page 115
... Shaded cells are not used by PORTE. Note 1: The RE3 port bit is available as an input-only pin only in 40-pin devices and when Master Clear functionality is disabled (CONFIG3H<7>=0). © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Function (1) Input/output port pin, analog input or read control input in Parallel Slave Port mode. ...
Page 116
... PIC18F2220/2320/4220/4320 10.6 Parallel Slave Port Note: The Parallel Slave Port is only available on PIC18F4X20 devices. In addition to its function as a general I/O port, PORTD can also operate as an 8-bit wide Parallel Slave Port (PSP) or microprocessor port. PSP operation is con- trolled by the 4 upper bits of the TRISE register (Register 10-1) ...
Page 117
... RCIF PIE1 PSPIE ADIE RCIE IPR1 PSPIP ADIP RCIP ADCON1 — — VCFG1 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Bit 4 Bit 3 Bit 2 Bit 1 — RE3 ...
Page 118
... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 116 © 2007 Microchip Technology Inc. ...
Page 119
... Prescale value 000 = 1:2 Prescale value © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Figure 11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register (Register 11- readable and writable register that controls all the aspects of Timer0, including the prescale selection ...
Page 120
... PIC18F2220/2320/4220/4320 FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE OSC RA4/T0CKI/C1OUT pin 1 T0SE T0CS Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale. FIGURE 11-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE RA4/T0CKI/C1OUT F /4 OSC 0 pin 1 Programmable Prescaler T0SE ...
Page 121
... Shaded cells are not used by Timer0. Note 1: RA6 and RA7 are enabled as I/O pins depending on the oscillator mode selected in Configuration Word 1H. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 11.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed “ ...
Page 122
... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 120 © 2007 Microchip Technology Inc. ...
Page 123
... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Register 12-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON< ...
Page 124
... PIC18F2220/2320/4220/4320 12.1 Timer1 Operation Timer1 can operate in one of these modes: • timer • synchronous counter • asynchronous counter The operating mode is determined by the Clock Select bit, TMR1CS (T1CON<1>). FIGURE 12-1: TIMER1 BLOCK DIAGRAM TMR1IF Overflow TMR1 Interrupt Flag bit TMR1H T1OSC ...
Page 125
... Capacitor values are for design guidance only. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 12.3 Timer1 Oscillator Layout Considerations The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity ...
Page 126
... PIC18F2220/2320/4220/4320 12.4 Timer1 Interrupt The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing Timer1 interrupt enable bit, TMR1IE (PIE1<0>). ...
Page 127
... Shaded cells are not used by the Timer1 module. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 ; Preload TMR1 register pair ; for 1 second overflow ...
Page 128
... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 126 © 2007 Microchip Technology Inc. ...
Page 129
... T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 13.1 Timer2 Operation Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is readable and writable and is cleared on any device Reset ...
Page 130
... PIC18F2220/2320/4220/4320 13.2 Timer2 Interrupt The Timer2 module has an 8-bit Period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. FIGURE 13-1: ...
Page 131
... TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Figure 14 simplified block diagram of the Timer3 module. Register 14-1 shows the Timer3 Control register. This register controls the operating mode of the Timer3 module and sets the CCP clock source. ...
Page 132
... PIC18F2220/2320/4220/4320 14.1 Timer3 Operation Timer3 can operate in one of these modes: • timer • synchronous counter • asynchronous counter The operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). FIGURE 14-1: TIMER3 BLOCK DIAGRAM TMR3IF Overflow Interrupt Flag bit TMR3H T1OSC T1OSO/ ...
Page 133
... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 14.4 Resetting Timer3 Using a CCP Trigger Output If the CCP module is configured in Compare mode to generate a (CCP1M3:CCP1M0 = 1011), this signal will reset Timer3. See Section 15.4.4 “ ...
Page 134
... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 132 © 2007 Microchip Technology Inc. ...
Page 135
... Compare mode: trigger special event (CCPxIF bit is set) 11xx = PWM mode © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Note: In 28-pin devices, both CCP1 and CCP2 function as standard CCP modules. In 40-pin devices, CCP1 is implemented as an Enhanced CCP module, offering addi- tional capabilities in PWM mode ...
Page 136
... PIC18F2220/2320/4220/4320 15.1 CCP1 Module Capture/Compare/PWM Register 1 (CCPR1) is com- prised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. TABLE 15-1: CCP MODE - TIMER RESOURCE CCP Mode Timer Resource ...
Page 137
... CCP2 pin and Edge Detect CCP2CON<3:0> Q’s © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 15.3.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit, CCP1IF, following any such change in operating mode ...
Page 138
... PIC18F2220/2320/4220/4320 15.4 Compare Mode In Compare mode, the 16-bit CCPR1 (CCPR2) register value is constantly compared against either the TMR1 register pair value, or the TMR3 register pair value. When a match occurs, the RC2/CCP1/P1A (RC1/T1OSI/CCP2) pin: • Is driven high • Is driven low • Toggles output (high-to-low or low-to-high) • ...
Page 139
... T3CKPS1 T3CKPS0 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1. Note 1: These bits are reserved on the PIC18F2X20 devices; always maintain these bits clear. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Bit 4 Bit 3 Bit 2 Bit 1 INT0IE ...
Page 140
... PIC18F2220/2320/4220/4320 15.5 PWM Mode In Pulse Width Modulation (PWM) mode, the CCP1 pin produces 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level ...
Page 141
... Shaded cells are not used by PWM and Timer2. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 15.5.3 SETUP FOR PWM OPERATION ...
Page 142
... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 140 © 2007 Microchip Technology Inc. ...
Page 143
... These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPR1L. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 The ECCP module differs from the CCP with the addi- tion of an enhanced PWM mode which allows for output channels, user-selectable polarity, dead band control and automatic shutdown and restart ...
Page 144
... PIC18F2220/2320/4220/4320 REGISTER 16-1: CCP1CON: ECCP CONTROL REGISTER (40/44-PIN DEVICES) (CONTINUED) bit 3-0 CCP1M3:CCP1M0: ECCP Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCP module) 0001 = Unused (reserved) 0010 = Compare mode, toggle output on match (CCP1IF bit is set) 0011 = Unused (reserved) 0100 = Capture mode, every falling edge ...
Page 145
... Note: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock or 2 bits of the prescaler to create the 10-bit time base. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 waveforms do not exactly match the standard PWM waveforms but are instead offset by one full instruction cycle ( ...
Page 146
... PIC18F2220/2320/4220/4320 FIGURE 16-2: PWM OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) SIGNAL CCP1CON <7:6> P1A Modulated (Single Output) 00 P1A Modulated (Half-Bridge) P1B Modulated 10 P1A Active P1B Inactive (Full-Bridge, 01 Forward) P1C Inactive P1D Modulated P1A Inactive P1B Modulated (Full-Bridge, 11 Reverse) P1C Active P1D Inactive FIGURE 16-3: ...
Page 147
... P1A and P1B as outputs. FIGURE 16-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) PIC18F4220/4320 Half-Bridge Output Driving a Full-Bridge Circuit PIC18F4220/4320 P1A P1B © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 FIGURE 16-4: Period Duty Cycle (2) P1A td (2) P1B ( Dead Band Delay Note 1: At this time, the TMR2 register is equal to the PR2 register ...
Page 148
... PIC18F2220/2320/4220/4320 16.4.3 FULL-BRIDGE MODE In Full-Bridge Output mode, four pins are used as out- puts; however, only two outputs are active at a time. In the Forward mode, pin RC2/CCP1/P1A is continuously active and pin RD7/PSP7/P1D is modulated. In the Reverse mode, RD6/PSP6/P1C pin is continuously active and RD5/PSP5/P1B pin is modulated. These are illustrated in Figure 16-6 ...
Page 149
... The direction of the PWM output changes when the duty cycle of the output near 100%. 2. The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 V+ QA FET Driver Load FET ...
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... PIC18F2220/2320/4220/4320 FIGURE 16-8: PWM DIRECTION CHANGE SIGNAL P1A (Active High) P1B (Active High) P1C (Active High) P1D (Active High) DC Note 1: The direction bit in the CCP1 Control register (CCP1CON<7>) is written any time during the PWM cycle. 2: When changing directions, the P1A and P1C signals switch before the end of the current PWM cycle at intervals of ...
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... PDC6:PDC0: PWM Delay Count bits Delay time, in number of F should transition to active and the actual time it transitions active. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 A shutdown event can be caused by either of the two comparator modules or the INT0 pin (or any combina- tion of these three sources). The comparators may be used to monitor a voltage input proportional to a current being monitored in the bridge circuit ...
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... PIC18F2220/2320/4220/4320 REGISTER 16-3: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN CONTROL REGISTER R/W-0 R/W-0 R/W-0 ECCPASE ECCPAS2 ECCPAS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 ECCPASE: ECCP Auto-Shutdown Event Status bit shutdown event has occurred; ECCP outputs are in shutdown state ...
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... Dead Time Duty Cycle Shutdown Event ECCPASE bit © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 16.4.6 START-UP CONSIDERATIONS When the ECCP module is used in the PWM mode, the application hardware must use the proper external pull- up and/or pull-down resistors on the PWM output pins. ...
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... PIC18F2220/2320/4220/4320 16.4.7 SETUP FOR PWM OPERATION The following steps should be taken when configuring the ECCP module for PWM operation: 1. Configure the PWM pins P1A and P1B (and P1C and P1D, if used) as inputs by setting the corresponding TRISC and TRISD bits. 2. Set the PWM period by loading the PR2 register. ...
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... PWM1CON PRSEN PDC6 PDC5 OSCCON IDLEN IRCF2 IRCF1 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the ECCP module in enhanced PWM mode. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Bit 4 Bit 3 Bit 2 Bit 1 INT0IE RBIE TMR0IF INT0IF POR ...
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... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 154 © 2007 Microchip Technology Inc. ...
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... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 17.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received, simultaneously. All four modes of ...
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... PIC18F2220/2320/4220/4320 17.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: • MSSP Control Register 1 (SSPCON1) • MSSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer (SSPBUF) • MSSP Shift Register (SSPSR) – Not directly accessible SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation ...
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... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When the MSSP is enabled in SPI mode, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 R/W-0 R/W-0 R/W-0 (2) (3) CKP ...
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... PIC18F2220/2320/4220/4320 17.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: • Master mode (SCK is the clock output) • Slave mode (SCK is the clock input) • ...
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... Shift Register (SSPSR) LSb MSb PROCESSOR 1 © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 17.3.4 TYPICAL CONNECTION Register 17-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their pro- grammed clock edge and latched on the opposite edge of the clock ...
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... PIC18F2220/2320/4220/4320 17.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 17- broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be dis- abled (programmed as an input) ...
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... SSPIF Interrupt Flag SSPSR to SSPBUF © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 is tri-stated, even if in the middle of a transmitted byte. External pull-up/pull-down resistors may be desirable, depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON1<3:0> = 0100), the SPI module will reset when the SS pin is set high ...
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... PIC18F2220/2320/4220/4320 FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) ...
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... Shaded cells are not used by the MSSP in SPI mode. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 17.3.8.1 Slave in Power-Managed Modes In Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device ...
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... PIC18F2220/2320/4220/4320 2 17 Mode 2 The MSSP module mode fully implements all master and slave functions (including general call sup- port) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master func- tion). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing ...
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... Start bit, Stop bit or not ACK bit. 4: ORing this bit with the SSPCON2 bits, SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 2 C™ MODE) R-0 R-0 ...
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... PIC18F2220/2320/4220/4320 REGISTER 17-4: SSPCON1: MSSP CONTROL REGISTER 1 (I R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 WCOL: Write Collision Detect bit In Master Transmit mode write to the SSPBUF register was attempted while the I ...
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... Clock stretching is enabled for both Slave Transmit and Slave Receive (stretch enabled Clock stretching is disabled Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 2 C™ MODE) R/W-0 R/W-0 ...
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... PIC18F2220/2320/4220/4320 17.4.2 OPERATION The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON1<5>). The SSPCON1 register allows control of the I ation. Four mode selection bits (SSPCON1<3:0>) allow 2 one of the following I C modes to be selected: 2 • Master mode, clock = F /(4 * (SSPADD + 1)) ...
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... The clock must be released by setting bit, CKP (SSPCON1<4>). See Section 17.4.4 “Clock Stretching” for more detail. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 17.4.3.3 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...
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... PIC18F2220/2320/4220/4320 2 FIGURE 17-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS39599G-page 170 © 2007 Microchip Technology Inc. ...
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... FIGURE 17-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 DS39599G-page 171 ...
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... PIC18F2220/2320/4220/4320 2 FIGURE 17-10: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS39599G-page 172 © 2007 Microchip Technology Inc. ...
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... FIGURE 17-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 DS39599G-page 173 ...
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... PIC18F2220/2320/4220/4320 17.4.4 CLOCK STRETCHING Both 7 and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence ...
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... DX SCL CKP WR SSPCON1 © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 remain low until the CKP bit is set and all other 2 devices on the I C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 17-12) ...
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... PIC18F2220/2320/4220/4320 2 FIGURE 17-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS39599G-page 176 © 2007 Microchip Technology Inc. ...
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... FIGURE 17-14: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 DS39599G-page 177 ...
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... PIC18F2220/2320/4220/4320 17.4.5 GENERAL CALL ADDRESS SUPPORT 2 The addressing procedure for the I C bus is such that the first byte after the Start condition usually deter- mines which device will be the slave addressed by the master. The exception is the general call address, which can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledge ...
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... FIGURE 17-16: MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Note: The MSSP module, when configured Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPBUF register to initiate transmission before the Start condi- tion is complete ...
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... PIC18F2220/2320/4220/4320 2 17.4.6 Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I not be released ...
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... Actual clock rate will depend on bus conditions. Bus capacitance can increase rise time and extend the low time of the clock period, reducing the effective clock frequency (see Section 17.4.7.2 “Clock Arbitration”). © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 17.4.7.1 Baud Rate Generation in ...
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... PIC18F2220/2320/4220/4320 17.4.7.2 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the ...
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... FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 17.4.8.1 WCOL Status Flag If the user writes the SSPBUF when a Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). ...
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... PIC18F2220/2320/4220/4320 2 17.4 MASTER MODE REPEATED START CONDITION TIMING A Repeated Start condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I module is in the Idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sam- pled low, the Baud Rate Generator is loaded with the contents of SSPADD< ...
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... WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 17.4.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowl- edge (ACK = 1) ...
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... PIC18F2220/2320/4220/4320 2 FIGURE 17-21: I C™ MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) DS39599G-page 186 © 2007 Microchip Technology Inc. ...
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... FIGURE 17-22: I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 DS39599G-page 187 ...
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... PIC18F2220/2320/4220/4320 17.4.12 ACKNOWLEDGE SEQUENCE TIMING An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable (SSPCON2<4>). When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to gen- erate an Acknowledge, then the ACKDT bit should be cleared ...
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... FIGURE 17-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA SCL BCLIF © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 17.4.17 MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION 2 C module Multi-Master mode support is achieved by bus arbitra- tion. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘ ...
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... PIC18F2220/2320/4220/4320 17.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) SDA or SCL is sampled low at the beginning of the Start condition (Figure 17-26). b) SCL is sampled low before SDA is asserted low (Figure 17-27). During a Start condition, both the SDA and the SCL pins are monitored ...
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... BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION Less than T SDA pulled low by other master. SDA Reset BRG and assert SDA. SCL SEN BCLIF S SSPIF © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 SDA = 0, SCL = BRG BRG SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SDA = 0, SCL = 1 Set S Set SSPIF ...
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... PIC18F2220/2320/4220/4320 17.4.17.2 Bus Collision During a Repeated Start Condition During a Repeated Start condition, a bus collision occurs if low level is sampled on SDA when SCL goes from low level to high level. b) SCL goes low before SDA is asserted low, indi- cating that another master is attempting to transmit a data ‘1’. ...
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... PEN BCLIF P SSPIF © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled ...
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... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 194 © 2007 Microchip Technology Inc. ...
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... TRISC<6> bit must be cleared (= 0) Register 18-1 shows the Transmit Status and Control register (TXSTA) and Register 18-2 shows the Receive Status and Control register (RCSTA). © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 18.1 Asynchronous Operation in Power-Managed Modes The USART may operate in Asynchronous mode while the peripheral clocks are being provided by the internal oscillator block ...
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... PIC18F2220/2320/4220/4320 REGISTER 18-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 CSRC TX9 TXEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care. Synchronous mode Master mode (clock generated internally from BRG) ...
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... OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 R/W-0 R/W-0 R-0 CREN ADDEN FERR U = Unimplemented bit, read as ‘ ...
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... PIC18F2220/2320/4220/4320 18.2 USART Baud Rate Generator (BRG) The BRG supports both the Asynchronous and Synchronous modes of the USART dedicated 8-bit Baud Rate Generator. The SPBRG register controls the period of a free-running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA<2>) also con- trols the baud rate. In Synchronous mode, bit BRGH is ignored ...