PIC18F2220-I/SP Microchip Technology, PIC18F2220-I/SP Datasheet - Page 251

• Manufacturer Part Number: PIC18F2220-I/SP
• Description: IC MCU FLASH 2KX16 A/D 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2220-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 4KB (2K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI/I2C/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

23.4
The Fail-Safe Clock Monitor (FSCM) allows the micro-
controller to continue operation, in the event of an
external oscillator failure, by automatically switching
the system clock to the internal oscillator block. The
FSCM function is enabled by setting the Fail-Safe
Clock Monitor Enable bit, FCMEN (CONFIG1H<6>).
When FSCM is enabled, the INTRC oscillator runs at
all times to monitor clocks to peripherals and provide
an instant backup clock in the event of a clock failure.
Clock monitoring (shown in Figure 23-3) is accom-
plished by creating a sample clock signal, which is the
INTRC output divided by 64. This allows ample time
between FSCM sample clocks for a peripheral clock
edge to occur. The peripheral system clock and the
sample clock are presented as inputs to the Clock Mon-
itor latch (CM). The CM is set on the falling edge of the
system clock source but cleared on the rising edge of
the sample clock.
FIGURE 23-3:
Clock failure is tested on the falling edge of the sample
clock. If a sample clock falling edge occurs while CM is
still set, a clock failure has been detected (Figure 23-4).
This causes the following:
• The FSCM generates an oscillator fail interrupt by
• The system clock source is switched to the
• The WDT is reset
Since the postscaler frequency from the internal oscil-
lator block may not be sufficiently stable, it may be
desirable to select another clock configuration and
enter an alternate power-managed mode (see
Section 23.3.1 “Special Considerations for Using
Two-Speed Start-up” and Section 3.1.3 “Multiple
Sleep Commands” for more details). This can be
done to attempt a partial recovery or execute a
controlled shutdown.
© 2007 Microchip Technology Inc.
Peripheral
setting bit, OSCFIF (PIR2<7>)
internal oscillator block (OSCCON is not updated
to show the current clock source – this is the
fail-safe condition)
(32 μs)
Source
INTRC
Clock
Fail-Safe Clock Monitor
(2.048 ms)
488 Hz
÷ 64
FSCM BLOCK DIAGRAM
(edge-triggered)
Clock Monitor
Latch (CM)
C
S
Q
Q
Detected
PIC18F2220/2320/4220/4320
Failure
Clock
To use a higher clock speed on wake-up, the INTOSC
or postscaler clock sources can be selected to provide
a higher clock speed by setting bits IFRC2:IFRC0
immediately after Reset. For wake-ups from Sleep, the
INTOSC or postscaler clock sources can be selected
by setting IFRC2:IFRC0 prior to entering Sleep mode.
Adjustments to the internal oscillator block using the
OSCTUNE register also affect the period of the FSCM
by the same factor. This can usually be neglected, as
the clock frequency being monitored is generally much
higher than the sample clock frequency.
The FSCM will detect failures of the primary or second-
ary clock sources only. If the internal oscillator block
fails, no failure would be detected, nor would any action
be possible.
23.4.1
Both the FSCM and the WDT are clocked by the
INTRC oscillator. Since the WDT operates with a sep-
arate divider and counter, disabling the WDT has no
effect on the operation of the INTRC oscillator when the
FSCM is enabled.
As already noted, the clock source is switched to the
INTOSC clock when a clock failure is detected.
Depending on the frequency selected by the
IRCF2:IRCF0 bits, this may mean a substantial change
in the speed of code execution. If the WDT is enabled
with a small prescale value, a decrease in clock speed
allows a WDT time-out to occur and a subsequent
device Reset. For this reason, fail-safe clock events
also reset the WDT and postscaler, allowing it to start
timing from when execution speed was changed and
decreasing the likelihood of an erroneous time-out.
FSCM AND THE WATCHDOG TIMER
DS39599G-page 249