PIC18F2220-I/SP Microchip Technology, PIC18F2220-I/SP Datasheet - Page 207

• Manufacturer Part Number: PIC18F2220-I/SP
• Description: IC MCU FLASH 2KX16 A/D 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2220-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 4KB (2K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI/I2C/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

To set up an Asynchronous Transmission:
1.
2.
3.
4.
FIGURE 18-5:
TABLE 18-7:
© 2007 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
SPBRG
Legend: x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1:
Name
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (Section 18.2 “USART Baud
Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
bit, SYNC, and setting bit, SPEN.
If interrupts are desired, set enable bit, TXIE.
If 9-bit transmission is desired, set Transmit bit,
TX9. Can be used as address/data bit.
Note:
RX (pin)
Rcv Shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word,
causing the OERR (Overrun) bit to be set.
USART Receive Register
Baud Rate Generator Register
GIE/GIEH
PSPIF
PSPIE
PSPIP
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
(1)
(1)
(1)
Start
ASYNCHRONOUS RECEPTION
bit
PEIE/
ADIE
ADIP
Bit 6
GIEL
ADIF
RX9
TX9
bit 0
TMR0IE INT0IE
bit 1
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
CREN ADDEN FERR
SYNC
Bit 4
TXIF
TXIE
TXIP
bit 7/8
PIC18F2220/2320/4220/4320
Stop
bit
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000
SSPIP CCP1IP TMR2IP TMR1IP 1111 1111
RBIE
Bit 3
—
Word 1
RCREG
Start
bit
TMR0IF INT0IF
BRGH
Bit 2
bit 0
5.
6.
7.
8.
Enable the transmission by setting bit, TXEN,
which will also set bit, TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
Load data to the TXREG register (starts
transmission).
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
OERR
TRMT
Bit 1
bit 7/8
Word 2
RCREG
Stop
RX9D
TX9D
RBIF
Bit 0
bit
Start
bit
0000 000x
0000 000x
0000 0000
0000 -010
0000 0000
POR, BOR
Value on
bit 7/8
DS39599G-page 205
0000 000u
0000 0000
0000 0000
1111 1111
0000 000x
0000 0000
0000 -010
0000 0000
Stop
bit
Value on
all other
Resets