T89C5115-TISUM Atmel, T89C5115-TISUM Datasheet - Page 67
![IC 8051 MCU FLASH 16K 28SOIC](/photos/6/82/68295/453-28-soic_sml.jpg)
T89C5115-TISUM
Manufacturer Part Number
T89C5115-TISUM
Description
IC 8051 MCU FLASH 16K 28SOIC
Manufacturer
Atmel
Series
89Cr
Datasheet
1.T89C5115-RATIM.pdf
(113 pages)
Specifications of T89C5115-TISUM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
20
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
89C5115-TISUM
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Watchdog Timer
Figure 31. Watchdog Timer
4128G–8051–02/08
Fwd Clock
RESET
WDTPRG
-
T89C5115 contains a powerful programmable hardware Watchdog Timer (WDT) that
automatically resets the chip if it software fails to reset the WDT before the selected time
interval has elapsed. It permits large Timeout ranging from 16ms to 2s @f
in X1 mode.
This WDT consists of a 14-bit counter plus a 7-bit programmable counter, a Watchdog
Timer reset register (WDTRST) and a Watchdog Timer programming (WDTPRG) regis-
ter. When exiting reset, the WDT is -by default- disable.
To enable the WDT, the user has to write the sequence 1EH and E1H into WDTRST
register with no instruction between the two writes. When the Watchdog Timer is
enabled, it will increment every machine cycle while the oscillator is running and there is
no way to disable the WDT except through reset (either hardware reset or WDT over-
flow reset). When WDT overflows, it will generate an output RESET pulse at the RST
pin. The RESET pulse duration is 96xT
the WDT, it should be serviced in those sections of code that will periodically be exe-
cuted within the time required to prevent a WDT reset
Note:
-
-
When the watchdog is enable it is impossible to change its period.
WDTRST
-
14-bit Counter
Enable
-
2
1
0
WR
OSC
Control
Decoder
, where T
7-bit Counter
Outputs
OSC
=1/f
OSC
. To make the best use of
RESET
OSC
= 12 MHz
67
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