T89C5115 ATMEL Corporation, T89C5115 Datasheet
T89C5115
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T89C5115 Summary of contents
Page 1
... ISP capability or with software. The programming voltage is internally generated from the standard VCC pin. The T89C5115 retains all features of the 80C52 with 256 bytes of internal RAM source 4-level interrupt controller and three timer/counters. In addition, the T89C5115 has a 10-bit A/D converter, a 2-KB Boot Flash memory, 2-KB EEPROM for data, a ...
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... Block Diagram XTAL1 XTAL2 CPU Notes analog Inputs/8 Digital I/O 2. 2-Bit I/O Port T89C5115 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time. EEPROM RAM Flash Boot UART 256x8 16kx8 loader 2kx8 C51 CORE IB-bus Timer 0 Parallel I/O Ports & Ext. Bus ...
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... VSS 11 12 VCC P3.2/INT0 17 13 XTAL1 P3.1/TxD 16 14 XTAL2 P3.0/RxD P3.7 7 PLCC- P3.5/ P3.4/ P3.3/INT1 QFP-32 P3 P3.5/ P3.4/ P3.3/INT1 8 17 T89C5115 P1.3/AN3/CEX0 P1.4/AN4/CEX1 P1.5/AN5 P1.6/AN6 P1.7/AN7 P2.0 RESET P1.3/AN3/CEX0 P1.4/AN4/CEX1 P1.5/AN5/CEX2 P1.6/AN6/CEX3 P1.7/AN7/CEX4 P2.0 NC RESET 3 ...
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... T89C5115 4 Table 1. Pin Description Pin Name Type Description VSS GND Circuit ground VCC Supply Voltage VAREF Reference Voltage for ADC VAVCC Supply Voltage for ADC VAGND Reference Ground for ADC P1.0:7 I/O Port 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins can be used for digital input/output or as analog inputs for the Analog Digital Converter (ADC). Port 1 pins that have 1’ ...
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... To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate above a frequency of 16 MHz, a duty cycle of 50% should be maintained. XTAL2: XTAL2 O Output from the inverting oscillator amplifier. , see section "Electrical Characteristic") because of the internal IL T89C5115 5 ...
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... I/O Configurations Port Structure T89C5115 6 Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A CPU "write to latch" signal initiates transfer of internal bus data into the type-D latch. A CPU "read latch" signal transfers the latched Q output onto the internal bus. Similarly, a " ...
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... Port latch. A logical one at the Port pin turns on pFET #3 (a weak pull-up) through the inverter. This inverter and pFET pair form a latch to drive logical one. pFET # very weak pull-up switched on whenever the T89C5115 Example ANL P1, A ...
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... T89C5115 8 associated nFET is switched off. This is traditional CMOS switch convention. Current strengths are 1/10 that of pFET #3 Figure 2. Internal Pull-Up Configurations 2 Osc. PERIODS OUTPUT DATA INPUT DATA READ PIN VCC VCC VCC p2 p1(1) p3 P1.x P2.x P3.x P4.x n 4128A–8051–04/02 ...
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... CDh byte Timer/Counter 2 Low TL2 CCh byte Timer/Counter 0 and TCON 88h 1 control Timer/Counter 0 and TMOD 89h 1 Modes 4128A–8051–04/02 The Special Function Registers (SFRs) of the T89C5115 fall into the following categories – – – – – – – ...
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... PCA Timer/Counter Mode 1 CCAP0H FAh PCA Compare Capture Module 0 H CCAP1H FBh PCA Compare Capture Module 1 H CCAP0L EAh PCA Compare Capture Module 0 L CCAP1L EBh PCA Compare Capture Module 1 L T89C5115 TF2 EXF2 RCLK – – – – – ...
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... ADAT6 – – – SMOD1 SMOD0 – – – ENBOOT – WDX2 PCAX2 FPL3 FPL2 FPL1 EEPL3 EEPL2 EEPL1 EEPL0 T89C5115 ET1 EX1 ET0 – – – EADC PS PT1 PX1 PT0 PSH PT1H PX1H PT0H – – – ...
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... Reserved Note: 1. These registers are bit-addressable. Sixteen addresses in the SFR space are both byte-addressable and bit-addressable. The bit-addressable SFR’s are those whose address ends in 0 and 8. The bit addresses, in this area, are 0x80 through to 0xFF. T89C5115 12 2/A 3/B 4/C CCAP0H CCAP1H 0000 0000 ...
Page 13
... Clock Description 4128A–8051–04/02 The T89C5115 core needs only 6 clock periods per machine cycle. This feature, called ‘X2’, provides the following advantages: • Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power. • Saves power consumption while keeping the same CPU power (oscillator power saving). • ...
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... Figure 3. Clock CPU Generation Diagram Hardware byte XTAL1 XTAL2 PD PCON.1 ÷ CKCON.0 T89C5115 14 X2B PCON.0 On RESET IDL X2 CKCON.0 ÷ ÷ 2 ÷ ÷ ÷ WDX2 PCAX2 SIX2 T2X2 CKCON.6 CKCON.5 CKCON.4 CKCON.3 CPU Core Clock CPU ...
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... For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. A UART with a 4800 baud rate will have a 9600 baud rate. 4128A–8051–04/02 X2 Mode T89C5115 STD Mode 15 ...
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... Register T89C5115 16 Table 12. CKCON Register CKCON (S:8Fh) Clock Control Register – WDX2 PCAX2 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. WatchDog clock 6 WDX2 Clear to select 6 clock periods per peripheral clock cycle. ...
Page 17
... Prevent Flash Corruption 4128A–8051–04/02 Two power reduction modes are implemented in the T89C5115: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 mode detailed in Section “ ...
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... Idle mode. The contents of the status of the Port pins during Idle mode is detailed in Table 13. To enter Idle mode, set the IDL bit in PCON register (see Table 14). The T89C5115 enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed ...
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... Program execution momentarily resumes with the instruction immediately following the instruction that activated Power-down mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the T89C5115 and vectors the CPU to address 0000h. Notes: 1. During the time that execution resumes, the internal RAM cannot be accessed ...
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... Registers T89C5115 20 PCON (S:87h) Table 14. PCON Register Power Configuration Register – – – Bit Bit Number Mnemonic Description Reserved 7-4 – The value read from these bits is indeterminate. Do not set these bits. General-purpose flag 1 3 GF1 One use is to indicate whether an interrupt occurred during normal operation or during Idle mode ...
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... Data Memory Internal Space Lower 128 Bytes RAM 4128A–8051–04/02 The T89C5115 provides data memory access in two different spaces: The internal space mapped in three separate segments: • the lower 128 bytes RAM segment. • the upper 128 bytes RAM segment. ...
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... Upper 128 Bytes RAM Expanded RAM T89C5115 22 Figure 8. Lower 128 bytes Internal RAM Organization 30h 20h 18h 10h 08h 00h The upper 128 bytes of RAM are accessible from address 80h to FFh using only indirect addressing mode. The on-chip 256 bytes of expanded RAM (ERAM) are accessible from address 0000h to 00FFh using indirect addressing mode through MOVX instructions ...
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... Description Application 4128A–8051–04/02 The T89C5115 implements a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR0 and DPTR1 are seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Figure 17) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (see Figure 9) ...
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... Registers T89C5115 24 Table 16. PSW Register PSW (S:8Eh) Program Status Word Register Bit Bit Number Mnemonic Description Carry Flag 7 CY Carry out from bit 1 of ALU operands. Auxiliary Carry Flag 6 AC Carry out from bit 1 of addition operands ...
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... This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3 flag. 1 – Reserved for Data Pointer Extension. Data Pointer Select Bit 0 DPS Set to select second dual data pointer: DPTR1. Clear to select first dual data pointer: DPTR0. Reset Value = xxxx 00x0b T89C5115 – GF3 0 – 0 DPS ...
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... Memory Write Data in the Column Latches Programming Read Data T89C5115 26 The 2-kbyte on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/ERAM memory space and is selected by setting control bits in the EECON register. A read in the EEPROM memory is done with a MOVX instruction. A physical write in the EEPROM memory is done in two steps: write data in the column latches and transfer of all data latches into an EEPROM memory row (programming) ...
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... EEPROM is not BUSY ;*************************************************************************** api_ld_eeprom_cl: MOV EECON, #02h ; map EEPROM in XRAM space MOVX @DPTR, A MOVEECON, #00h; unmap EEPROM ret ;*F************************************************************************* ;* NAME: api_wr_eeprom ;* NOTE: before execute this function, be sure the EEPROM is not BUSY ;*************************************************************************** api_wr_eeprom: MOV EECON, #050h MOV EECON, #0A0h ret T89C5115 27 ...
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... Registers T89C5115 28 Table 18. EECON Register EECON (S:0D2h) EEPROM Control Register EEPL3 EEPL2 EEPL1 Bit Bit Number Mnemonic Description Programming Launch Command bits 7-4 EEPL3-0 Write 5Xh followed by AXh to EEPL to launch the programming. Reserved 3 - The value read from this bit is indeterminate. Do not set this bit. ...
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... Extra Row (128 bytes) Column Latches (128 bytes) 4128A–8051–04/02 The T89C5115 implement 16-KB of on-chip program/code memory. The Flash memory increases EPROM and ROM functionality by in-circuit electrical era- sure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is generated on-chip using the standard VDD volt- age ...
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... User Space Extra Row (XROW) Hardware security Byte Column Latches Cross Flash Memory Access Description T89C5115 30 The Flash memory is made blocks (see Figure 11): 1. The memory array (user space) 16-KB. 2. The Extra Row. 3. The Hardware security bits. 4. The column latch registers. ...
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... Security A X Byte 5 X Reserved A X Note: The sequence 5xh and Axh must be executing without instructions between them other- wise the programming is aborted. T89C5115 FM0 Adressable space User (0000h-3FFFh) Extra Row(FF80h-FFFFh) Hardware Security Byte (0000h) reserved FMOD1 FMOD0 Operation action ...
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... Status of the Flash Memory Selecting FM1 Loading the Column Latches T89C5115 32 Interrupts that may occur during programming time must be disabled to avoid any spuri- ous exit of the programming mode. The bit FBUSY in FCON register is used to indicate the status of programming. FBUSY is set when programming is in progress. ...
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... The end of the programming indicated by the FBUSY flag cleared. • Enable the interrupts. Column Latches Loading Save & Disable IT EA= 0 Column Latches Mapping FCON = 08h (FPS=1) Data Load DPTR= Address ACC= Data Exec: MOVX @DPTR, A Last Byte to load? Data memory Mapping FCON = 00h (FPS = 0) Restore IT T89C5115 33 ...
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... Hardware Security Byte T89C5115 34 Figure 13. Flash and Extra row Programming Procedure The following procedure is used to program the Hardware and is summarized in Figure 14: • Set FPS and map Hardware byte (FCON = 0x0C) • Save and disable the interrupts. • Load DPTR at address 0000h. ...
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... Map the Hardware Security space by writing 04h in FCON register. • Read the byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 & DPTR= 0000h. • Clear FCON to unmap the Hardware Security Byte. T89C5115 Save & Disable IT EA= 0 Launch Programming FCON= 54h FCON= A4h ...
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... Flash Protection from Parallel Programming Preventing Flash Corruption T89C5115 36 Figure 15. Reading Procedure Flash Spaces Reading Exec: MOVC A, @A+DPTR The three lock bits in Hardware Security Byte (see "In-System Programming" section) are programmed according to Table 22 provide different level of protection for the on- chip code and data located in FM0 and FM1 ...
Page 37
... Clear to re-map the data memory space. Flash Mode 2-1 FMOD1:0 See Table 20 or Table 21. Flash Busy Set by hardware when programming is in progress. 0 FBUSY Clear by hardware when programming is done. Can not be changed by software. Reset Value = 0000 0000b T89C5115 FPL0 FPS FMOD1 FMOD0 1 0 FBUSY 37 ...
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... With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash technology the T89C5115 allows the system engineer the development of applications with a very high level of flexibility. This flexibility is based on the possibility to alter the customer program at any stages of a product’s life: • ...
Page 39
... These bytes are reserved for customer use read or modify these bytes, the APIs are used. Figure 17. Hardware Boot Process Algorithm ENBOOT = 0000h Application Boot Loader in FM0 bit ENBOOT in AUXR1 register RESET is initialized with BLJB. BLJB == 0 ? ENBOOT = F800h in FM1 T89C5115 39 ...
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... Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All calls are made by functions. All APIs are describe in: "In-System Programing: Flash Library for T89C5115", available on the Atmel web site at www.atmel.com. Table 23. List of API ...
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... To start the boot loader(@F800h) located in FM1. Reserved 5-3 - The value read from these bits are indeterminate. 2-0 LB2:0 Lock Bits Default value after erasing chip: FFh Notes: 1. Only the 4 MSB bits can be accessed by software. 2. The 4 LSB bits can only be accessed by parallel mode. T89C5115 LB2 LB1 0 LB0 41 ...
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... Framing Error Detection T89C5115 42 The T89C5115 I/O serial port is compatible with the I/O serial port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously ...
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... To support automatic address recognition, a device is identified by a given address and a broadcast address. Note: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect Data byte Data byte T89C5115 Stop bit D8 Ninth Stop bit bit 43 ...
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... Given Address Broadcast Address T89C5115 44 Each device has an individual address that is specified in the SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time ...
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... Figure 21 in the other modes. Reset Value = 0000 0000b Bit addressable REN TB8 RB8 Mode Baud Rate Shift Register F /12 ( mode X2) XTAL XTAL 8-bit UART Variable 9-bit UART F / /32 XTAL XTAL 9-bit UART Variable T89C5115 ...
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... T89C5115 46 Table 27. SADEN Register SADEN (S:B9h) Slave Address Mask Register Bit Bit Number Mnemonic Description 7-0 – Mask Data for Slave Individual Address Reset Value = 0000 0000b Not bit addressable Table 28. SADDR Register SADDR (S:A9h) Slave Address Register Bit Bit ...
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... Power-down mode bit 1 PD Cleared by hardware when reset occurs. Set to enter power-down mode. Idle mode bit 0 IDL Clear by hardware when interrupt or reset occurs. Set to enter idle mode. Reset Value = 00x1 0000b Not bit addressable T89C5115 POF GF1 GF0 IDL 47 ...
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... Timer 0 T89C5115 48 The T89C5115 implements two general-purpose, 16-bit Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. ...
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... TRx TCON reg Mode 1 configures Timer 16-bit Timer with TH0 and TL0 registers connected in cascade (see Figure 23). The selected input increments TL0 register. 0 THx (8 bits) 1 TRx TCON reg T89C5115 Timer x TLx Overflow Interrupt TFx (5 bits) Request TCON reg Timer x TLx ...
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... FTx ÷ 6 CLOCK see section “Clock” T89C5115 50 Mode 2 configures Timer 8-bit Timer (TL0 register) that automatically reloads from TH0 register (see Figure 24). TL0 overflow sets TF0 flag in TCON register and reloads TL0 with the contents of TH0, which is preset by software. When the interrupt request is serviced, hardware clears TF0 ...
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... TL1 with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged. Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt Timer 1 when TR1 run control bit is not available i.e. when Timer mode 3. T89C5115 51 ...
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... Interrupt T89C5115 52 Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This flag is set every time an overflow occurs. Flags are cleared when vectoring to the Timer interrupt routine. Interrupts are enabled by setting interrupts are globally enabled by setting EA bit in IEN0 register. ...
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... Set by hardware when external interrupt is detected on INT0# pin. Interrupt 0 Type Control Bit 0 IT0 Clear to select low level active (level triggered) for external interrupt 0 (INT0#). Set to select falling edge active (edge triggered) for external interrupt 0. Reset Value = 0000 0000b T89C5115 TR0 IE1 IT1 ...
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... T89C5115 54 Table 32. TMOD Register TMOD (S:89h) Timer/Counter Mode Control Register GATE1 C/T1# M11 Bit Bit Number Mnemonic Description Timer 1 Gating Control Bit 7 GATE1 Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set. ...
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... Number Mnemonic Description 7:0 Low Byte of Timer 0. Reset Value = 0000 0000b Table 35. TH1 Register TH1 (S:8Dh) Timer 1 High Byte Register Bit Bit Number Mnemonic Description 7:0 High Byte of Timer 1. Reset Value = 0000 0000b T89C5115 ...
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... T89C5115 56 Table 36. TL1 Register TL1 (S:8Bh) Timer 1 Low Byte Register Bit Bit Number Mnemonic Description 7:0 Low Byte of Timer 1. Reset Value = 0000 0000b 4128A–8051–04/02 ...
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... CLOCK T2 4128A–8051–04/02 The T89C5115 Timer 2 is compatible with Timer 2 in the 80C52 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 that are cascade- connected controlled by T2CON register (See Table ) and T2MOD register (See Table 39). Timer 2 operation is similar to Timer 0 and Timer 1 ...
Page 58
... Output Figure 28. Clock-out Mode FT2 CLOCK T2EX T89C5115 58 In clock-out mode, Timer 2 operates as a 50%-duty-cycle, programmable clock genera- tor (See Figure 28). The input clock increments TL2 at frequency F repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, Timer 2 overflows do not generate interrupts ...
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... Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on Timer 2 overflow. 0 CP/RL2# Clear to auto-reload on Timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1. Reset Value = 0000 0000b Bit addressable T89C5115 TCLK EXEN2 TR2 C/T2 CP/RL2# ) ...
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... T89C5115 60 Table 38. T2MOD Register T2MOD (S:C9h) Timer 2 Mode Control Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...
Page 61
... High Byte of Timer 2 Reload/Capture. Reset Value = 0000 0000b Not bit addressable Table 42. RCAP2L Register RCAP2L (S: Timer 2 Reload/Capture Low Byte Register Bit Bit Number Mnemonic Description 7-0 Low Byte of Timer 2 Reload/Capture. Reset Value = 0000 0000b Not bit addressable T89C5115 ...
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... Fwd Clock - T89C5115 62 T89C5115 contains a powerful programmable hardware WatchDog Timer (WDT) that automatically resets the chip if it software fails to reset the WDT before the selected time interval has elapsed. It permits large Time-Out ranking from 16ms to 2s @Fosc = 12 MHz in X1 mode. This WDT consists of a 14-bit counter plus a 7-bit programmable counter, a WatchDog Timer reset register (WDTRST) and a WatchDog Timer programming (WDTPRG) regis- ter ...
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... The following table indicates the computed Time-Out value for Fosc mode Table 44. Time-Out Computation T89C5115 S0 Machine Cycle Count ...
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... WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting T89C5115 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode. ...
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... WDTRST (S:A6h Write only) WatchDog Timer Enable Register Bit Bit Number Mnemonic Description 7 - WatchDog Control Value Reset Value = 1111 1111b Note: The WDRST register is used to reset/enable the WDT by writing 1EH then E1H in sequence without instruction between these two sequences. T89C5115 ...
Page 66
... Programmable Counter Array (PCA) PCA Timer T89C5115 66 The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules ...
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... ECF bit in CMOD register is set. The CF bit can only be cleared by software. • The CCF0:1 bits are the flags for the modules (CCF0 for module0...) and are set by hardware when either a match or a capture occurs. These flags also can be cleared by software. T89C5115 To PCA modules overflow CH ...
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... PCA Modules T89C5115 68 Each one of the five compare/capture modules has six possible functions. It can perform: • 16-bit Capture, positive-edge triggered • 16-bit Capture, negative-edge triggered • 16-bit Capture, both positive and negative-edge triggered • 16-bit Software Timer • 16-bit High Speed Output • ...
Page 69
... PCA counter registers (CH and CL) into the module’s capture reg- isters (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated. 0CAPPn CAPNn000 ECCFn 7 CCAPMn Register ( T89C5115 CCON CCF1 CCF0 0xD8 To Interrupt EA EC IEN0.7 IEN0 ...
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... Write to “1” CCAPnL Write to CCAPnH T89C5115 70 The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module’s capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set ...
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... When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. the allows the PWM to be updated with- out glitches. The PWM and ECOM bits in the module’s CCAPMn register must be set to enable the PWM mode. T89C5115 CCON CCF1 CCF0 0xD8 ...
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... Figure 35. PCA PWM Mode CL rolls over from FFh TO 00h loads CCAPnH contents into CCAPnL CL (8 bits) T89C5115 72 CCAPnH CCAPnL “0” CL < CCAPnL 8-Bit Comparator CL >= CCAPnL “1” ECOMn PWMn CCAPMn.6 CCAPMn.1 CEX 4128A–8051–04/02 ...
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... Enable PCA Counter Overflow Interrupt bit 0 ECF Clear to disable CF bit in CCON register to generate an interrupt. Set to enable CF bit in CCON register to generate an interrupt. Reset Value = 00XX X000b CPS1 Internal Clock, FPca/6 Internal Clock, FPca/2 Timer 0 overflow External clock at ECI/P1.2 pin (Max. Rate = FPca/4) T89C5115 1 0 CPS0 ECF 73 ...
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... T89C5115 74 Table 48. CCON Register CCON (S:D8h) PCA Counter Control Register Bit Bit Number Mnemonic Description PCA Timer/Counter Overflow flag Set by hardware when the PCA Timer/Counter rolls over. This generates a PCA 7 CF interrupt request if the ECF bit in CMOD register is set. ...
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... PCA Low Byte Compare/Capture Module n Register (n=0.. CCAPnL 7 CCAPnL 6 CCAPnL 5 Bit Bit Number Mnemonic Description CCAPnL 7:0 Low byte of EWC-PCA comparison or capture values 7:0 Reset Value = 0000 0000b CCAPnH 4 CCAPnH 3 CCAPnH 2 CCAPnH CCAPnL 4 CCAPnL 3 CCAPnL 2 CCAPnL 1 T89C5115 1 0 CCAPnH CCAPnL 0 75 ...
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... T89C5115 76 Table 51. CCAPMn Registers CCAPM0 (S:DAh) CCAPM1 (S:DBh) PCA Compare/Capture Module n Mode registers (n=0.. ECOMn CAPPn Bit Bit Number Mnemonic Description Reserved 7 - The Value read from this bit is indeterminate. Do not set this bit. Enable Compare Mode Module x bit Clear to disable the Compare function. ...
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... Reset Value = 0000 00000b Table 53. CL Register CL (S:E9h) PCA counter Register Low Value Bit Bit Number Mnemonic Description 7:0 CL0 7:0 Low byte of Timer/Counter Reset Value = 0000 00000b T89C5115 ...
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... ADC Port1 I/O Functions T89C5115 78 This section describes the on-chip 10-bit analog-to-digital converter of the T89C5115. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC converter to select one from the 8 ADC chan- nels as ADC input voltage (ADCIN). ADCIN is converted by the 10 bit-cascaded potentiometric ADC ...
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... Figure 37 shows the timing diagram of a complete conversion. For simplicity, the figure depicts the waveforms in idealized form and do not provide precise timing information. For ADC characteristics and timing parameters refer to the Section “AC Characteristics” of the T89C5115 datasheet. T CONV A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3). ...
Page 80
... Voltage Conversion Clock Selection Figure 38. A/D Converter Clock CPU CLOCK CPU Core Clock Symbol ADC Standby Mode T89C5115 80 Table 54. Selected Analog Input SCH2 SCH1 When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If the input voltage equals VAGND, the ADC converts it to 000h ...
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... Start a precision conversion (need interrupt ADC) // The variable "channel" contains the channel to convert // Enable ADC EADC = 1 // clear the field SCH[2:0] ADCON &= F8h // Select the channel ADCON |= channel // Start conversion in precision mode ADCON |= 48h Note: to enable the ADC interrupt T89C5115 ADCI EADC IEN1.1 81 ...
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... Registers T89C5115 82 Table 55. ADCF Register ADCF (S:F6h) ADC Configuration Bit Bit Number Mnemonic Description Channel Configuration 7-0 CH 0:7 Set to use P1.x as ADC input. Clear to use P1.x as standart I/O port. Reset Value = 0000 0000b Table 56. ADCON Register ADCON (S:F3h) ADC Control Register ...
Page 83
... The value read from these bits are indeterminate. Do not set these bits. ADC result 1-0 ADAT1:0 bits 1-0 Reset Value = 00h PRS 4 PRS 3 PRS ADAT 6 ADAT 5 ADAT 4 ADAT ADAT 1 T89C5115 1 0 PRS 1 PRS ADAT ADAT 0 83 ...
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... UART RxD Timer 2 ADC AIN1:0 T89C5115 84 The T89C5115 has a total of 8 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), a serial port interrupt, a PCAand an ADC. These interrupts are shown below. EX0 IEN0.0 ET0 IEN0.1 EX1 IEN0 ...
Page 85
... Table 61. Interrupt Priority Within Level Interrupt Name Interrupt Address Vector external interrupt (INT0) Timer0 (TF0) external interrupt (INT1) Timer1 (TF1) PCA (CF or CCFn) UART (RI or TI) Timer2 (TF2) ADC (ADCI) T89C5115 IPL.x Interrupt Level Priority 0 0 (Lowest (Highest) Priority Number ...
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... Registers T89C5115 86 Table 62. IEN0 Register IEN0 (S:A8h) Interrupt Enable Register ET2 Bit Bit Number Mnemonic Description Enable All interrupt bit Clear to disable all interrupts Set to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. ...
Page 87
... The value read from this bit is indeterminate. Do not set this bit. ADC Interrupt Enable bit 1 EADC Clear to disable the ADC interrupt. Set to enable the ADC interrupt. Reserved 0 - The value read from this bit is indeterminate. Do not set this bit. Reset Value = xxxx xx0xb bit addressable T89C5115 EADC ...
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... T89C5115 88 Table 64. IPL0 Register IPL0 (S:B8h) Interrupt Enable Register PPC PT2 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt Priority bit 6 PPC Refer to PPCH for priority level. Timer 2 overflow interrupt Priority bit ...
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... The value read from this bit is indeterminate. Do not set this bit. ADC Interrupt Priority level less significant bit. 1 PADCL Refer to PSPIH for priority level. Reserved 0 - The value read from this bit is indeterminate. Do not set this bit. Reset Value = xxxx xx0xb bit addressable T89C5115 PADCL 0 - ...
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... T89C5115 90 Table 66. IPL0 Register IPH0 (B7h) Interrupt High Priority Register PPCH PT2H Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt Priority level most significant bit PPCH PPC Priority level ...
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... The value read from this bit is indeterminate. Do not set this bit. ADC Interrupt Priority level most significant bit PADCH PADCL PADCH Reserved 0 - The value read from this bit is indeterminate. Do not set this bit. Reset Value = xxxx xx0xb T89C5115 PADCH Priority level Lowest Highest ...
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... Power-down I is measured with all output pins disconnected; XTAL2 NC.; RST = V CC WDT must be inactive and the POF flag must be set. 4. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature. T89C5115 92 Note ± 10 MHz ...
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... SIGNAL V SS Figure 43. I Test Condition, Power-down Mode RST (NC) XTAL2 XTAL1 V SS T89C5115 must be externally limited as fol- OL may exceed the related specification. Pins are All other pins are disconnected All other pins are disconnected. ...
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... DC Parameters for A/D Converter T89C5115 94 Figure 44. Clock Signal Waveform for I V -0.5V CC 0.45V T CHCL T Table 69. DC Parameters for AD Converter in Precision conversion Symbol Parameter AVin Analog input voltage Rref Resistance between Vref and Vss Vref Reference voltage Cai Analog input Capacitance INL Integral non linearity ...
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... Serial port clock cycle time Output data set-up to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid Min Max 300 200 30 0 117 T89C5115 Units ...
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... Shift Register Timing Waveforms INSTRUCTION ALE CLOCK T OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI External Clock Drive Characteristics (XTAL1) External Clock Drive Waveforms AC Testing Input/Output Waveforms T89C5115 96 Table 72. AC Parameters for a Variable Clock Symbol Type T Min XLXL T Min QVHX T Min XHQX T ...
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... OL OH Table 74. Memory AC Timing VDD = 5V ± 10 -40 to +85°C Symbol Parameter T Flash Internal Busy (Programming) Time BHBL Figure 45. Flash Memory - Internal Busy Waveforms FBUSY bit FLOAT LOAD LOAD V - 0.1 V LOAD Min Typ 10 T BHBL T89C5115 /V level OH OL Max Unit ms 97 ...
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... Ordering Information Table 75. Possible Order Entries Memory Size Part-Number T89C5115-SISIM 16K T89C5115-TISIM 16K T89C5115-RATIM 16K T89C5115 98 Temperature Supply Voltage Range 5V Industrial 5V Industrial 5V Industrial Max Frequency Package 40 MHz PLCC28 40 MHz SOIC28 40 MHz VQFP32 Packing Stick Stick Tray 4128A–8051–04/02 ...
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... Package Drawing PLCC28 4128A–8051–04/02 T89C5115 99 ...
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... Package Drawing SOIC28 T89C5115 100 4128A–8051–04/02 ...
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... Package Drawing VQFP32 4128A–8051–04/02 T89C5115 101 ...
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... Reset Recommendation to Prevent Flash Corruption ........................................ 17 Idle Mode ............................................................................................................ 18 Power-down Mode.............................................................................................. 18 Registers..............................................................................................................20 Data Memory ....................................................................................... 21 Internal Space..................................................................................................... 21 Dual Data Pointer ............................................................................................... 23 Registers............................................................................................................. 24 EEPROM Data Memory ....................................................................... 26 Write Data in the Column Latches ...................................................................... 26 Programming ...................................................................................................... 26 Read Data........................................................................................................... 26 Examples ............................................................................................................ 27 Registers............................................................................................................. 28 Program/Code Memory ...................................................................... 29 Flash Memory Architecture................................................................................. 29 Overview of FM0 Operations .............................................................................. 31 Registers............................................................................................................. 37 T89C5115 i ...
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... T89C5115 ii In-System Programming (ISP) ........................................................... 38 Flash Programming and Erasure ........................................................................ 38 Boot Process ...................................................................................................... 39 Application Programming Interface..................................................................... 40 XROW Bytes....................................................................................................... 40 Hardware Security Byte ...................................................................................... 41 Serial I/O Port ...................................................................................... 42 Framing Error Detection .................................................................................... 42 Automatic Address Recognition.......................................................................... 43 Given Address ..................................................................................................... 44 Broadcast Address ............................................................................................. 44 Registers............................................................................................................. 45 Timers/Counters ................................................................................. 48 Timer/Counter Operations .................................................................................. 48 Timer 0................................................................................................................ 48 Timer 1................................................................................................................. 51 Interrupt ...............................................................................................................52 Registers............................................................................................................. 53 Timer 2 ................................................................................................. 57 Auto-reload Mode ...
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... IT ADC Management ...........................................................................................81 Routine Examples............................................................................................... 81 Registers..............................................................................................................82 Interrupt System ................................................................................. 84 Introduction ......................................................................................................... 84 Registers............................................................................................................. 86 Electrical Characteristics ................................................................... 92 Absolute Maximum Ratings ................................................................................ 92 DC Parameters for Standard Voltage ................................................................. 92 DC Parameters for A/D Converter ...................................................................... 94 AC Parameters ....................................................................................................95 Ordering Information .......................................................................... 98 Package Drawing ................................................................................ 99 PLCC28 .............................................................................................................. 99 Package Drawing .............................................................................. 100 SOIC28 ............................................................................................................. 100 Package Drawing .............................................................................. 101 VQFP32 ............................................................................................................ 101 T89C5115 iii ...
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... Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...