T89C5115-TISUM Atmel, T89C5115-TISUM Datasheet - Page 36

• Manufacturer Part Number: T89C5115-TISUM
• Description: IC 8051 MCU FLASH 16K 28SOIC
• Manufacturer: Atmel
• Series: 89Cr

Specifications of T89C5115-TISUM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 20
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 89C5115-TISUM

Programming the Flash Spaces
User
Extra Row
36
AT89C5115
Figure 14. Column Latches Loading Procedure
Note:
The following procedure is used to program the User space and is summarized in
Figure 15:
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The following procedure is used to program the Extra Row space and is summarized in
Figure 15:
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Load up to one page of data in the column latches from address 0000h to 3FFFh.
Save then disable the interrupts.
Launch the programming by writing the data sequence 50h followed by A0h in
FCON register.This step must be executed from FM1.
The end of the programming indicated by the FBUSY flag cleared.
Restore the interrupts.
Load data in the column latches from address FF80h to FFFFh.
Save then disable the interrupts.
Launch the programming by writing the data sequence 52h followed by A2h in
FCON register. This step of the procedure must be executed from FM1.
The end of the programming indicated by the FBUSY flag cleared.
Restore the interrupts.
1. The last page address used when loading the column latch is the one used to select
the page programming address.
Column Latches Mapping
Exec: MOVX @DPTR, A
FCON = 08h (FPS = 1)
Data Memory Mapping
FCON = 00h (FPS = 0)
Column Latches
Save & Disable IT
DPTR = Address
ACC = Data
Last Byte
Data Load
to load?
Restore IT
Loading
EA = 0
(1)
4128G–8051–02/08