R5F21134DFP#U0 Renesas Electronics America, R5F21134DFP#U0 Datasheet - Page 71

• Manufacturer Part Number: R5F21134DFP#U0
• Description: IC R8C MCU FLASH 32LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/13r

Specifications of R5F21134DFP#U0

• Core Size: 16-Bit
• Program Memory Size: 16KB (16K x 8)
• Oscillator Type: Internal
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• No. Of I/o's: 22
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1024Byte
• Cpu Speed: 20MHz
• No. Of Timers: 16
• Digital Ic Case: RoHS Compliant
• Controller Family/series: R8C/13
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13R0E521134EPB00 - KIT EMULATOR PROBE FOR PC7501R0E521134CPE00 - EMULATOR COMPACT R8C/13
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

R8C/13 Group
Rev.1.20
REJ09B0111-0120
Figure 10.8 Hardware Interrupt Priority
Reset > WDT/Oscillation stop detection/Voltage detection > Peripheral function > Single step > Address match
• Returning from an Interrupt Routine
• Interrupt Priority
Jan 27, 2006
The FLG register and PC in the state in which they were immediately before entering the interrupt
sequence are restored from the stack by executing the REIT instruction at the end of the interrupt
routine. Thereafter the CPU returns to the program which was being executed before accepting the
interrupt request.
Return the other registers saved by a program within the interrupt routine using the POPM or similar
instruction before executing the REIT instruction.
If two or more interrupt requests are generated while executing one instruction, the interrupt request
that has the highest priority is accepted.
For maskable interrupts (peripheral functions), any desired priority level can be selected using the
ILVL2 to ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their
interrupt priority is resolved by hardware, with the highest priority interrupt accepted.
The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 10.8
shows the Hardware Interrupt Priority.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control
branches invariably to the interrupt routine.
page 58 of 205
10.1 Interrupt Overview