R5F21134DFP#U0 Renesas Electronics America, R5F21134DFP#U0 Datasheet - Page 44

• Manufacturer Part Number: R5F21134DFP#U0
• Description: IC R8C MCU FLASH 32LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/13r

Specifications of R5F21134DFP#U0

• Core Size: 16-Bit
• Program Memory Size: 16KB (16K x 8)
• Oscillator Type: Internal
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 22
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• No. Of I/o's: 22
• Eeprom Memory Size: 4KB
• Ram Memory Size: 1024Byte
• Cpu Speed: 20MHz
• No. Of Timers: 16
• Digital Ic Case: RoHS Compliant
• Controller Family/series: R8C/13
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13R0E521134EPB00 - KIT EMULATOR PROBE FOR PC7501R0E521134CPE00 - EMULATOR COMPACT R8C/13
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

R8C/13 Group
Rev.1.20
REJ09B0111-0120
Figure 6.2 CM0 Register and CM1 Register
b 7
b7
S y s t e m c l o c k c o n t r o l r e g i s t e r 0
0
System clock control register 1
N O T E S :
N O T E S :
1 . S e t t h e P R C 0 b i t o f P R C R r e g i s t e r t o “ 1 ” ( w r i t e e n a b l e ) b e f o r e w r i t i n g t o t h i s r e g i s t e r .
2 . T h e C M 0 5 b i t i s p r o v i d e d t o s t o p t h e m a i n c l o c k w h e n t h e o n - c h i p o s c i l l a t o r m o d e i s s e l e c t e d . T h i s b i t c a n n o t b e u s e d f o r d e t e c t i o n
3 . S e t t h e C M 0 5 b i t t o “ 1 ” ( m a i n c l o c k s t o p s ) a n d t h e C M 1 3 b i t i n t h e C M 1 r e g i s t e r t o “ 1 ” ( X
4 . W h e n t h e C M 0 5 b i t i s s e t t o “ 1 ” ( m a i n c l o c k s t o p ) , P 4
5 . W h e n e n t e r i n g s t o p m o d e f r o m h i g h o r m i d d l e s p e e d m o d e , t h e C M 0 6 b i t i s s e t t o “ 1 ” ( d i v i d e - b y - 8 m o d e ) .
1 . W r i t e t o t h i s r e g i s t e r a f t e r s e t t i n g t h e P R C 0 b i t o f P R C R r e g i s t e r t o “ 1 ” ( w r i t e e n a b l e ) .
2 . W h e n e n t e r i n g s t o p m o d e f r o m h i g h o r m i d d l e s p e e d m o d e , t h e C M 1 5 b i t i s s e t t o “ 1 ” ( d r i v e c a p a c i t y h i g h ) .
3 . E f f e c t i v e w h e n t h e C M 0 6 b i t i s “ 0 ” ( C M 1 6 a n d C M 1 7 b i t s e n a b l e ) .
4 . I f t h e C M 1 0 b i t i s “ 1 ” ( s t o p m o d e ) , t h e i n t e r n a l f e e d b a c k r e s i s t o r b e c o m e s i n e f f e c t i v e .
5 . T h e C M 1 4 b i t c a n b e s e t t o “ 1 ” ( l o w - s p e e d o n - c h i p o s c i l l a t o r o f f ) i f t h e O C D 2 b i t = 0 ( m a i n c l o c k s e l e c t e d ) . W h e n t h e O C D 2 b i t i s
6 . W h e n u s i n g v o l t a g e d e t e c t i o n i n t e r r u p t c i r c u i t , C M 1 4 b i t i s s e t t o “ 0 ”
7 . W h e n t h e C M 1 0 b i t i s s e t t o “ 1 ” ( s t o p m o d e ) o r t h e C M 0 5 b i t i n t h e C M 0 r e g i s t e r t o “ 1 ” ( m a i n c l o c k s t o p s ) a n d t h e C M 1 3 b i t i s s e t
b 6
b 6
a s t o w h e t h e r t h e m a i n c l o c k s t o p p e d o r n o t . T o s t o p t h e m a i n c l o c k , t h e f o l l o w i n g s e t t i n g i s r e q u i r e d :
( 1 ) S e t t h e O C D 0 a n d O C D 1 b i t s i n t h e O C D r e g i s t e r t o “ 0 0
( 2 ) S e t t h e O C D 2 b i t t o “ 1 ” ( o n - c h i p o s c i l l a t o r c l o c k s e l e c t i o n ) .
s e t t o “ 1 ” ( s e l e c t i n g o n - c h i p o s c i l l a t o r c l o c k ) , t h e C M 1 4 b i t i s s e t t o “ 0 ” ( l o w - s p e e d o n - c h i p o s c i l l a t o r o n ) . T h i s b i t r e m a i n s
u n c h a n g e d w h e n “ 1 ” i s w r i t t e n .
t o “ 1 ” ( X
W h e n t h e C M 1 3 b i t i s s e t t o “ 0 ” ( i n p u t p o r t s P 4
Jan 27, 2006
b 5
b 5
b 4
b 4
0
I N
b 3
b 3
- X
1
O U T
b2
b 2
0 0
p i n ) , t h e X
b 1
b 1
0 0
page 31 of 205
b0
b 0
B i t s y m b o l
B i t s y m b o l
( b 1 - b 0 )
O U T
C M 0 2
C M 0 5
C M 1 5
C M 1 6
C M 1 7
C M 0 6
C M 1 4
C M 1 0
C M 1 3
( b 1 )
( b 2 )
(b3)
(b4)
( b 7 )
S y m b o l
C M 1
S y m b o l
C M 0
( P 4
7
) p i n b e c o m e s “ H ” .
(1)
( 1 )
A l l c l o c k s t o p c o n t r o l b i t
C P U c l o c k d i v i s i o n
s e l e c t b i t 1
Reserved bit
Reserved bit
Port X
L o w - s p e e d o n - c h i p
o s c i l l a t i o n s t o p b i t
X
s e l e c t b i t
R e s e r v e d b i t
W A I T p e r i p h e r a l f u n c t i o n
c l o c k s t o p b i t
M a i n c l o c k ( X
b i t
C P U c l o c k d i v i s i o n s e l e c t
b i t 0
R e s e r v e d b i t
R e s e r v e d b i t
R e s e r v e d b i t
I N
(2 , 4 )
- X
(5 )
O U T
IN
-X
(2)
6
Bit name
B i t n a m e
d r i v e c a p a c i t y
OUT
(3)
P 4
7
A d d r e s s
A d d r e s s
I N
switch bit
6
0 0 0 6
0 0 0 7
) t h e P 4
- X
a n d P 4
(5 , 6 )
O U T
1 6
1 6
2
” ( d i s a b l e o s c i l l a t i o n s t o p d e t e c t i o n f u n c t i o n ) .
) s t o p
7
(4 , 7 )
7
(7)
c a n b e u s e d a s i n p u t p o r t s .
( X
O U T
A f t e r r e s e t
A f t e r r e s e t
0 : C l o c k o n
1 : A l l c l o c k s o f f ( s t o p m o d e )
S e t t o
S e t t o
0 : I n p u t p o r t P 4
1 : X
0 : L o w - s p e e d o n - c h i p o s c i l l a t o r o n
1 : L o w - s p e e d o n - c h i p o s c i l l a t o r o f f
0 0 : N o d i v i s i o n m o d e
0 1 : D i v i s i o n b y 2 m o d e
1 0 : D i v i s i o n b y 4 m o d e
1 1 : D i v i s i o n b y 1 6 m o d e
Set to “0”
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode
Set to “1”
Set to “0”
0 : On
1 : Off
0 : CM16 and CM17 valid
1 : Divide-by-8 mode
Set to “0”
b7 b6
0 : L O W
1 : H I G H
) e n t e r s i n p u t m o d e
6 8
2 0
I N
1 6
1 6
(3)
- X
“ 0 ”
“ 0 ”
O U T
p i n
6
, P 4
I N
7
- X
F u n c t i o n
F u n c t i o n
O U T
p i n ) w h e n t h e e x t e r n a l c l o c k i s i n p u t .
6. Clock Generating Circuit
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W