R5F21122FP#U0 Renesas Electronics America, R5F21122FP#U0 Datasheet - Page 196

• Manufacturer Part Number: R5F21122FP#U0
• Description: IC R8C MCU FLASH 8K 32LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/12r

Specifications of R5F21122FP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: LED, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13R0E521134EPB00 - KIT EMULATOR PROBE FOR PC7501R0E521134CPE00 - EMULATOR COMPACT R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.
1.10 Apr.27.2005
1.20 Jan.27.2006
Date
REVISION HISTORY
Page
142
147
150
152
158
160
165
166
168
169
173
174
7-8
10
12
13
15
17
20
22
24
28
32
37
11
2
3
4
6
9
Table 4.1 SFR Information(1) NOTES:1 revised
Table 4.2 SFR Information(2) NOTES:1 revised
Table 4.3 SFR Information(3);
0081
0082
0083
0085
0086
0087
008C
NOTES:1 revised
Table 4.4 SFR Information(4) NOTES:1 revised
Figure 5.2 Reset Sequence; “72cycles”
6 Clock Generation Circuit;
“(oscillation stop detect function)”
Table 6.1 Clock Generation Circuit Specifications NOTES: 2 deleted
Figure 6.3 OCD Register NOTES: 3 partly deleted
6.2 On-Chip Oscillator Clock;
“The application products ... to accommodate the frequency range.”
“The application products ... for the frequency change.” revised
Table 6.2 Setting Clock Related Bit and Modes CM13 added
6.5.1 How to Use Oscillation Stop Detection Function:
“This function cannot ... is below 2 MHz.” added
Table 9.1 Bus Cycles for Access Space, Table 9.2 Access Unit and Bus Operation;
“SFR”
ROM/RAM”
Table 10.2 Relocatable Vector Tables; “A/D”
“Product List”
Table 17.3 partly added
Figure 17.5 added
•Program partly revised
Figure 17.11 partly added
Figure 17.13 package name revised
18.1 partly revised
19.3.2 added
19.4.4 partly revised
19.6 partly revised
19.7.1 partly added
20 partly revised
Package Dimensions revised
Table 1.1 Performance outline revised
Figure 1.1 Block diagram partly revised
1.4 Product Information, title of Table 1.2
ROM capacity; “Program area”
Figure 1.2 Type No., Memory Size, and Package partly revised
Table 1.3 Pin description revised
2 Central Processing Unit (CPU) revised
Figure 2.1 CPU register revised
3 Memory, Figure 3.1 Memory Map;
“Program area”
16
16
16
16
16
16
16
: “Prescaler Y”
: “Timer Y Secondary”
: “Timer Y Primary”
: “Prescaler Z”
: “Timer Z Secondary”
: “Timer Z Primary”
: “Prescaler X”
“SFR, Data flash”,
“Program ROM/RAM” revised
“Data area”
“Product Informaton” revised
“Program ROM”, “Data area”
C-3
“Prescaler Z Register”
“Prescaler Y Register”
“Prescaler X Register” revised
“Timer Y Primary Register”
“Timer Z Primary Register”
Description
R8C/12 Group Hardware Manual
“Data flash” revised
“Timer Y Secondary Register”
“Timer Z Secondary Register”
“Program ROM”,
Summary
“(oscillation stop detection function)” revised
“64cycles” revised
“A/D Conversion” revised
“Data flash” revised