R5F21122FP#U0 Renesas Electronics America, R5F21122FP#U0 Datasheet - Page 133

• Manufacturer Part Number: R5F21122FP#U0
• Description: IC R8C MCU FLASH 8K 32LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/12r

Specifications of R5F21122FP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: LED, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13R0E521134EPB00 - KIT EMULATOR PROBE FOR PC7501R0E521134CPE00 - EMULATOR COMPACT R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/12 Group
Rev.1.20
REJ09B0110-0120
Figure 15.6 PD0 Register, PD1 Register, PD3 Register, and PD4 Register
Figure 15.7 P0 Register, P1 Register, P3 Register, and P4 Register
P o r t P i r e g i s t e r ( i = 0 , 1 , 3 , 4 )
P o r t P i d i r e c t i o n r e g i s t e r ( i = 0 , 1 , 3 , 4 )
b 7
b 7
N O T E S :
N O T E S :
Jan 27, 2006
1 . T h e P D 0 r e g i s t e r m u s t b e w r i t t e n t o b y t h e n e x t i n s t r u c t i o n a f t e r s e t t i n g t h e P R C 2 b i t i n t h e P R C R
2 . B i t s P D 3 _ 4 t o P D 3 _ 6 i n t h e P D 3 r e g i s t e r a r e u n a v a i l a b l e o n t h i s M C U . I f i t i s n e c e s s a r y t o s e t b i t s
3 . B i t s P D 4 _ 0 t o P D 4 _ 4 , P D 4 _ 6 a n d P D 4 _ 7 i n t h e P D 4 r e g i s t e r a r e u n a v a i l a b l e o n t h i s M C U . I f i t i s
1 . B i t s P 3 _ 4 t o P 3 _ 6 i n t h e P 3 r e g i s t e r a r e u n a v a i l a b l e o n t h i s M C U . I f i t i s n e c e s s a r y t o s e t b i t s P 3 _ 4 t o
2 . B i t s P 4 _ 0 t o P 4 _ 4 i n t h e P 4 r e g i s t e r a r e u n a v a i l a b l e o n t h i s M C U . I f i t i s n e c e s s a r y t o s e t b i t s P 4 _ 0 t o
b 6
b 6
r e g i s t e r t o “ 1 ” ( w r i t e e n a b l e d ) .
P D 3 _ 4 t o P D 3 _ 6 , s e t t o “ 0 ” ( i n p u t m o d e ) . W h e n r e a d , t h e c o n t e n t i s i n d e t e r m i n a t e .
n e c e s s a r y t o s e t b i t s P D 4 _ 0 t o P D 4 _ 4 , P D 4 _ 6 a n d P D 4 _ 7 , s e t t o “ 0 ” ( i n p u t m o d e ) . W h e n r e a d ,
t h e c o n t e n t i s i n d e t e r m i n a t e .
P 3 _ 6 , s e t t o “ 0 ” ( “ L ” l e v e l ) . W h e n r e a d , t h e c o n t e n t i s i n d e t e r m i n a t e .
P 4 _ 4 , s e t t o “ 0 ” ( “ L ” l e v e l ) . W h e n r e a d , t h e c o n t e n t i s i n d e t e r m i n a t e .
b 5
b 5
b 4
b 4
b3
b 3
b2
b 2
page 121 of 181
b 1
b 1
b 0
b 0
P i _ 0
P i _ 1
P i _ 2
P i _ 3
P i _ 4
P i _ 5
P i _ 6
P i _ 7
B i t s y m b o l
P D i _ 0
P D i _ 1
P D i _ 2
P D i _ 3
P D i _ 4
P D i _ 5
P D i _ 6
P D i _ 7
B i t s y m b o l
S y m b o l
P 0
P 1
P 3
P 4
S y m b o l
(1 , 2 )
P D 0
P D 1
P D 3
P D 4
P o r t P i
P o r t P i
P o r t P i
P o r t P i
P o r t P i
P o r t P i
P o r t P i
P o r t P i
P o r t P i
P o r t P i
P o r t P i
P o r t P i
P o r t P i
P o r t P i
P o r t P i
P o r t P i
0
1
2
3
4
5
6
7
Bit name
b i t
b i t
b i t
b i t
b i t
b i t
b i t
b i t
( 1 , 2 , 3 )
0
1
2
3
4
5
6
7
A d d r e s s
0 0 E 0
0 0 E 1
0 0 E 5
0 0 E 8
B i t n a m e
d i r e c t i o n b i t
d i r e c t i o n b i t
d i r e c t i o n b i t
d i r e c t i o n b i t
d i r e c t i o n b i t
d i r e c t i o n b i t
d i r e c t i o n b i t
d i r e c t i o n b i t
1 6
1 6
1 6
1 6
A d d r e s s
0 0 E 3
0 0 E A
0 0 E 2
0 0 E 7
The pin level on any I/O port which is
set for input mode can be read by
reading the corresponding bit in this
register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register
0 : “L” level
1 : “H” level
1 6
1 6
1 6
1 6
0 : I n p u t m o d e
1 : O u t p u t m o d e
( F u n c t i o n s a s a n i n p u t p o r t )
( F u n c t i o n s a s a n o u t p u t p o r t )
F u n c t i o n
I n d e t e r m i n a t e
I n d e t e r m i n a t e
I n d e t e r m i n a t e
F u n c t i o n
I n d e t e r m i n a t e
( i = 0 , 1 , 3 , 4 )
A f t e r r e s e t
15. Programmable I/O Ports
A f t e r r e s e t
0 0
0 0
0 0
0 0
1 6
1 6
1 6
1 6
RW
RW
RW
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W
R W