R5F21122FP#U0 Renesas Electronics America, R5F21122FP#U0 Datasheet - Page 103

IC R8C MCU FLASH 8K 32LQFP

R5F21122FP#U0

Manufacturer Part Number
R5F21122FP#U0
Description
IC R8C MCU FLASH 8K 32LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/R8C/Tiny/12r
Datasheets

Specifications of R5F21122FP#U0

Core Processor
R8C
Core Size
16-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
LED, WDT
Number Of I /o
22
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521134S000BE - KIT EVAL STARTER FOR R8C/13R0E521134EPB00 - KIT EMULATOR PROBE FOR PC7501R0E521134CPE00 - EMULATOR COMPACT R8C/13
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F21122FP#U0R5F21122FP#V0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/12 Group
Rev.1.20
REJ09B0110-0120
Figure 13.3 U0TB and U1TB Registers, U0RB and U1RB Registers, and U0BRG and U1BRG Registers
( b 1 5 )
NOTES:
b 7
1. Write to this register while serial interface is neither transmitting nor receiving.
2. Use MOV instruction to write to this register.
3. After setting the CLK0 to CLK1 bits of the UiC0 register, write to the UiBRG register.
U A R T i t r a n s m i t b u f f e r r e g i s t e r
U A R T i r e c e i v e b u f f e r r e g i s t e r
b 7
U A R T i b i t r a t e r e g i s t e r
b 7
( b 1 5 )
N O T E S :
1 . W h e n t r a n s f e r d a t a l e n g t h i s 9 - b i t l o n g , w r i t e h i g h - b y t e f i r s t t h e n l o w - b y t e .
2 . U s e M O V i n s t r u c t i o n t o w r i t e t o t h i s r e g i s t e r .
NOTES:
1. Read out the UiRB register in 16-bit unit.
2. All of the SUM, PER, FER and OER bits are set to “0” (no error) when the SMD2 to SMD0 bits in the UiMR register are set to “000
disabled) or the RE bit in the UiC1 register is set to “0” (reception disabled). The SUM bit is set to “0” (no error) when all of the PER, FER and OER
bits are set to “0” (no error).
The PER and FER bits are set to “0” even when the higher byte of the UiRB register is read.
Jan 27, 2006
( b 8 )
( b 8 )
b 0
b 0
b 0
b 7
b 7
page 91 of 181
( 1 , 2 , 3 )
( i = 0 , 1 )
(1 )
(1 , 2 )
( i = 0 , 1 )
( i = 0 , 1 )
(b15-b9)
(b11-b9)
s y m b o l
(b8-b0)
symbol
(b7-b0)
A s s u m i n g t h a t s e t v a l u e = n , U i B R G d i v i d e s t h e c o u n t s o u r c e
b y n + 1
OER
SUM
F E R
P E R
B i t
(b8)
Bit
b0
b0
T r a n s m i t d a t a
N o t h i n g i s a s s i g n e d .
W h e n w r i t e , s e t t o “ 0 ” . W h e n r e a d , i t s c o n t e n t i s i n d e t e r m i n a t e .
Overrun error flag
Framing error flag
Parity error flag
Error sum flag
N o t h i n g i s a s s i g n e d .
W h e n w r i t e , s e t t o “ 0 ” . W h e n r e a d , i t s c o n t e n t i s i n d e t e r m i n a t e .
Symbol
S y m b o l
U0TB
U1TB
U 0 B R G
U 1 B R G
S y m b o l
U 0 R B
U 1 R B
Bit name
(2)
(2)
00AB
(2)
00A3
0 0 A F
(2)
0 0 A 7
F u n c t i o n
Address
A d d r e s s
A d d r e s s
0 0 A 1
0 0 A 9
16
16
1 6
1 6
-00A2
-00AA
- 0 0 A 6
- 0 0 A E
1 6
1 6
0 : N o o v e r r u n e r r o r
1 : O v e r r u n e r r o r f o u n d
R e c e i v e d a t a ( D
Receive data (D
0 : N o f r a m i n g e r r o r
1 : F r a m i n g e r r o r f o u n d
0 : N o p a r i t y e r r o r
1 : P a r i t y e r r o r f o u n d
0 : No error
1 : Error found
16
16
1 6
1 6
Indeterminate
Indeterminate
I n d e t e r m i n a t e
I n d e t e r m i n a t e
I n d e t e r m i n a t e
I n d e t e r m i n a t e
Function
After reset
A f t e r r e s e t
A f t e r r e s e t
7
8
)
t o D
0
)
Function
S e t t i n g r a n g e
00
16
to FF
2
13. Serial Interfaces
” (serial interface
16
RW
W O
R W
RO
R O
RO
RO
R O
R O
RW
WO

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