C8051F321-GM Silicon Laboratories Inc, C8051F321-GM Datasheet - Page 147

• Manufacturer Part Number: C8051F321-GM
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321-GM

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: I2C/SMBus/SPI/UART/USB
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F320DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit or 17-ch x 10-bit
• No. Of I/o's: 21
• Ram Memory Size: 1280Byte
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1480 - DAUGHTER CARD TOOLSTCK C8051F321770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1449 - ADAPTER PROGRAM TOOLSTICK F321336-1260 - DEV KIT FOR C8051F320/F321
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1261

15.5. FIFO Management
1024 bytes of on-chip XRAM are used as FIFO space for USB0. This FIFO space is split between
Endpoints0-3 as shown in Figure 15.3. FIFO space allocated for Endpoints1-3 is configurable as IN, OUT,
or both (Split Mode: half IN, half OUT).
15.5.1. FIFO Split Mode
The FIFO space for Endpoints1-3 can be split such that the upper half of the FIFO space is used by the IN
endpoint, and the lower half is used by the OUT endpoint. For example: if the Endpoint3 FIFO is configured
for Split Mode, the upper 256 bytes (0x0540 to 0x063F) are used by Endpoint3 IN and the lower 256 bytes
(0x0440 to 0x053F) are used by Endpoint3 OUT.
If an endpoint FIFO is not configured for Split Mode, that endpoint IN/OUT pair’s FIFOs are combined to
form a single IN or OUT FIFO. In this case only one direction of the endpoint IN/OUT pair may be used at
a time. The endpoint direction (IN/OUT) is determined by the DIRSEL bit in the corresponding endpoint’s
EINCSRH register (see Figure 15.20).
0x07C0
0x07BF
0x07FF
0x073F
0x063F
0x043F
0x03FF
0x0740
0x0640
0x0440
0x0400
0x0000
(1024 bytes)
User XRAM
(128 bytes)
(256 bytes)
(512 bytes)
Figure 15.3. USB FIFO Allocation
Endpoint0
Endpoint1
Endpoint2
Endpoint3
(64 bytes)
(64 bytes)
Free
Rev. 1.4
USB Clock Domain
System Clock Domain
IN, OUT, or both (Split
Configurable as
Mode)
C8051F320/1
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